dec2812.map.qmsg

DSP2812开发板板上的CPLD源代码

{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D6 74273 inst7 " "Warning: Port \"D6\" of type 74273 and instance \"inst7\" is missing source signal" {  } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 800 592 712 992 "inst7" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D5 74273 inst7 " "Warning: Port \"D5\" of type 74273 and instance \"inst7\" is missing source signal" {  } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 800 592 712 992 "inst7" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D8 74273 inst7 " "Warning: Port \"D8\" of type 74273 and instance \"inst7\" is missing source signal" {  } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 800 592 712 992 "inst7" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D4 74273 inst22 " "Warning: Port \"D4\" of type 74273 and instance \"inst22\" is missing source signal" {  } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 2208 864 984 2400 "inst22" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D7 74273 inst22 " "Warning: Port \"D7\" of type 74273 and instance \"inst22\" is missing source signal" {  } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 2208 864 984 2400 "inst22" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D6 74273 inst22 " "Warning: Port \"D6\" of type 74273 and instance \"inst22\" is missing source signal" {  } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 2208 864 984 2400 "inst22" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D5 74273 inst22 " "Warning: Port \"D5\" of type 74273 and instance \"inst22\" is missing source signal" {  } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 2208 864 984 2400 "inst22" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Warning" "WGDFX_NO_SOURCE_FOR_PORT" "D8 74273 inst22 " "Warning: Port \"D8\" of type 74273 and instance \"inst22\" is missing source signal" {  } { { "DEC2812.bdf" "" { Schematic "D:/2812board_N/DEC2812.bdf" { { 2208 864 984 2400 "inst22" "" } } } }  } 0 0 "Port \"%1!s!\" of type %2!s! and instance \"%3!s!\" is missing source signal" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/others/maxplus2/74273.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/others/maxplus2/74273.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74273 " "Info: Found entity 1: 74273" {  } { { "74273.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74273.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74273 74273:inst2 " "Info: Elaborating entity \"74273\" for hierarchy \"74273:inst2\"" {  } { { "DEC2812.bdf" "inst2" { Schematic "D:/2812board_N/DEC2812.bdf" { { 520 592 712 712 "inst2" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/others/maxplus2/74244.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/others/maxplus2/74244.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74244 " "Info: Found entity 1: 74244" {  } { { "74244.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74244.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74244 74244:inst4 " "Info: Elaborating entity \"74244\" for hierarchy \"74244:inst4\"" {  } { { "DEC2812.bdf" "inst4" { Schematic "D:/2812board_N/DEC2812.bdf" { { 40 360 464 232 "inst4" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "f:/altera/quartus51/libraries/others/maxplus2/74138.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file f:/altera/quartus51/libraries/others/maxplus2/74138.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 74138 " "Info: Found entity 1: 74138" {  } { { "74138.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74138.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74138 74138:inst10 " "Info: Elaborating entity \"74138\" for hierarchy \"74138:inst10\"" {  } { { "DEC2812.bdf" "inst10" { Schematic "D:/2812board_N/DEC2812.bdf" { { 800 800 920 960 "inst10" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WOPT_MLS_CONVERT_TRI_TO_OR_HDR" "" "Warning: Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" { { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74244:inst4\|26 " "Warning: Converting TRI node \"74244:inst4\|26\" that feeds logic to a wire" {  } { { "74244.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74244.bdf" { { 432 296 344 464 "26" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74244:inst4\|27 " "Warning: Converting TRI node \"74244:inst4\|27\" that feeds logic to a wire" {  } { { "74244.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74244.bdf" { { 384 296 344 416 "27" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74244:inst4\|31 " "Warning: Converting TRI node \"74244:inst4\|31\" that feeds logic to a wire" {  } { { "74244.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74244.bdf" { { 336 296 344 368 "31" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74244:inst4\|36 " "Warning: Converting TRI node \"74244:inst4\|36\" that feeds logic to a wire" {  } { { "74244.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74244.bdf" { { 288 296 344 320 "36" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74244:inst4\|1 " "Warning: Converting TRI node \"74244:inst4\|1\" that feeds logic to a wire" {  } { { "74244.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74244.bdf" { { 64 296 344 96 "1" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74244:inst4\|6 " "Warning: Converting TRI node \"74244:inst4\|6\" that feeds logic to a wire" {  } { { "74244.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74244.bdf" { { 112 296 344 144 "6" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74244:inst4\|10 " "Warning: Converting TRI node \"74244:inst4\|10\" that feeds logic to a wire" {  } { { "74244.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74244.bdf" { { 160 296 344 192 "10" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0} { "Warning" "WOPT_MLS_CONVERT_TRI_TO_WIRE" "74244:inst4\|11 " "Warning: Converting TRI node \"74244:inst4\|11\" that feeds logic to a wire" {  } { { "74244.bdf" "" { Schematic "f:/altera/quartus51/libraries/others/maxplus2/74244.bdf" { { 208 296 344 240 "11" "" } } } }  } 0 0 "Converting TRI node \"%1!s!\" that feeds logic to a wire" 0 0}  } {  } 0 0 "Converted TRI buffer or tri-state bus to logic, or removed OPNDRN" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "145 " "Info: Implemented 145 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "27 " "Info: Implemented 27 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "37 " "Info: Implemented 37 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_BIDIRS" "8 " "Info: Implemented 8 bidirectional pins" {  } {  } 0 0 "Implemented %1!d! bidirectional pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "73 " "Info: Implemented 73 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 30 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 30 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Jul 26 16:59:42 2007 " "Info: Processing ended: Thu Jul 26 16:59:42 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}