📄 sram4m.fit.rpt
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Fitter report for sram4m
Mon Oct 20 16:40:32 2008
Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
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; Table of Contents ;
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1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Pin-Out File
5. Fitter Resource Usage Summary
6. Input Pins
7. Output Pins
8. Bidir Pins
9. I/O Bank Usage
10. All Package Pins
11. Output Pin Default Load For Reported TCO
12. Fitter Resource Utilization by Entity
13. Delay Chain Summary
14. Pad To Core Delay Chain Fanout
15. Control Signals
16. Global & Other Fast Signals
17. Non-Global High Fan-Out Signals
18. Interconnect Usage Summary
19. LAB Logic Elements
20. LAB Signals Sourced
21. LAB Signals Sourced Out
22. LAB Distinct Inputs
23. Fitter Device Options
24. Advanced Data - General
25. Advanced Data - Placement Preparation
26. Advanced Data - Placement
27. Advanced Data - Routing
28. Fitter Messages
29. Fitter Suppressed Messages
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; Legal Notice ;
----------------
Copyright (C) 1991-2007 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+------------------------------------------+
; Fitter Status ; Successful - Mon Oct 20 16:40:31 2008 ;
; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Full Version ;
; Revision Name ; sram4m ;
; Top-level Entity Name ; sram4m ;
; Family ; Cyclone ;
; Device ; EP1C6Q240C8 ;
; Timing Models ; Final ;
; Total logic elements ; 107 / 5,980 ( 2 % ) ;
; Total pins ; 88 / 185 ( 48 % ) ;
; Total virtual pins ; 0 ;
; Total memory bits ; 0 / 92,160 ( 0 % ) ;
; Total PLLs ; 0 / 2 ( 0 % ) ;
+-----------------------+------------------------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+
; Device ; EP1C6Q240C8 ; ;
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