📄 t_procedure.tan.rpt
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Classic Timing Analyzer report for t_procedure
Sun Feb 18 13:57:12 2007
Quartus II Version 6.1 Build 201 11/27/2006 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. tsu
6. tco
7. th
8. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+-------------+--------+--------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+-------------+--------+--------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 2.323 ns ; A ; C~reg0 ; -- ; clk ; 0 ;
; Worst-case tco ; N/A ; None ; 6.493 ns ; C~reg0 ; C ; clk ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -2.213 ns ; A ; C~reg0 ; -- ; clk ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+-------------+--------+--------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP1S10F780C5 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+--------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+--------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+--------+----------+
; N/A ; None ; 2.323 ns ; A ; C~reg0 ; clk ;
+-------+--------------+------------+------+--------+----------+
+--------------------------------------------------------------+
; tco ;
+-------+--------------+------------+--------+----+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+--------+----+------------+
; N/A ; None ; 6.493 ns ; C~reg0 ; C ; clk ;
+-------+--------------+------------+--------+----+------------+
+--------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+--------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+--------+----------+
; N/A ; None ; -2.213 ns ; A ; C~reg0 ; clk ;
+---------------+-------------+-----------+------+--------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 6.1 Build 201 11/27/2006 SJ Full Version
Info: Processing started: Sun Feb 18 13:57:12 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off t_procedure -c t_procedure --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "clk" is an undefined clock
Info: No valid register-to-register data paths exist for clock "clk"
Info: tsu for register "C~reg0" (data pin = "A", clock pin = "clk") is 2.323 ns
Info: + Longest pin to register delay is 5.087 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AC11; Fanout = 1; PIN Node = 'A'
Info: 2: + IC(3.681 ns) + CELL(0.319 ns) = 5.087 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'C~reg0'
Info: Total cell delay = 1.406 ns ( 27.64 % )
Info: Total interconnect delay = 3.681 ns ( 72.36 % )
Info: + Micro setup delay of destination is 0.010 ns
Info: - Shortest clock path from clock "clk" to destination register is 2.774 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AC10; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(1.145 ns) + CELL(0.542 ns) = 2.774 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'C~reg0'
Info: Total cell delay = 1.629 ns ( 58.72 % )
Info: Total interconnect delay = 1.145 ns ( 41.28 % )
Info: tco from clock "clk" to destination pin "C" through register "C~reg0" is 6.493 ns
Info: + Longest clock path from clock "clk" to source register is 2.774 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AC10; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(1.145 ns) + CELL(0.542 ns) = 2.774 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'C~reg0'
Info: Total cell delay = 1.629 ns ( 58.72 % )
Info: Total interconnect delay = 1.145 ns ( 41.28 % )
Info: + Micro clock to output delay of source is 0.156 ns
Info: + Longest register to pin delay is 3.563 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'C~reg0'
Info: 2: + IC(1.159 ns) + CELL(2.404 ns) = 3.563 ns; Loc. = PIN_W11; Fanout = 0; PIN Node = 'C'
Info: Total cell delay = 2.404 ns ( 67.47 % )
Info: Total interconnect delay = 1.159 ns ( 32.53 % )
Info: th for register "C~reg0" (data pin = "A", clock pin = "clk") is -2.213 ns
Info: + Longest clock path from clock "clk" to destination register is 2.774 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AC10; Fanout = 1; CLK Node = 'clk'
Info: 2: + IC(1.145 ns) + CELL(0.542 ns) = 2.774 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'C~reg0'
Info: Total cell delay = 1.629 ns ( 58.72 % )
Info: Total interconnect delay = 1.145 ns ( 41.28 % )
Info: + Micro hold delay of destination is 0.100 ns
Info: - Shortest pin to register delay is 5.087 ns
Info: 1: + IC(0.000 ns) + CELL(1.087 ns) = 1.087 ns; Loc. = PIN_AC11; Fanout = 1; PIN Node = 'A'
Info: 2: + IC(3.681 ns) + CELL(0.319 ns) = 5.087 ns; Loc. = LC_X33_Y1_N2; Fanout = 1; REG Node = 'C~reg0'
Info: Total cell delay = 1.406 ns ( 27.64 % )
Info: Total interconnect delay = 3.681 ns ( 72.36 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning
Info: Allocated 102 megabytes of memory during processing
Info: Processing ended: Sun Feb 18 13:57:12 2007
Info: Elapsed time: 00:00:00
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