eg2.vhd

matlab在fpga中的应用的三个具体事例

--例2． 使用变量和信号得到不同的结果

library IEEE;
use IEEE.std_logic_1164.all;

entity eg2 is
	port (
			a_bus 	: in  std_logic_vector(3 downto 0);
			carryout: out  std_logic
		 );
end entity; 

architecture a of eg2 is 
   signal tmp : std_logic; --信号的定义
begin
process(a_bus)
begin
    tmp <= '1';
    for i in 3 downto 0 loop
       tmp <= a_bus(i) and tmp; --信号的赋值
       end loop;
       carryout <= tmp;
   end process;
end a;