_pace.ucf

xilinx fpga 做VGA驱动信号的Verilog原代码,ise版本9.2

NET "clk"  LOC = "T9"  ;
#PACE: Start of Constraints generated by PACE

#PACE: Start of PACE I/O Pin Assignments
NET "clock"  LOC = "T9"  ; 
NET "vga_B"  LOC = "R11"  ;
NET "vga_G"  LOC = "T12"  ;
NET "vga_h_sync"  LOC = "R9"  ;
NET "vga_R"  LOC = "R12"  ;
NET "vga_v_sync"  LOC = "T10"  ;

#PACE: Start of PACE Area Constraints

#PACE: Start of PACE Prohibit Constraints

#PACE: End of Constraints generated by PACE