vgavga_map.map

xilinx fpga 做VGA驱动信号的Verilog原代码,ise版本9.2

Release 9.2i Map J.36
Xilinx Map Application Log File for Design 'vgavga'

Design Information
------------------
Command Line   : E:\Program Files\xp\Xilinx92i\bin\nt\map.exe -ise E:/Program
Files/xp/Xilinx92i/mydesign/vgavga/vgavga.ise -intstyle ise -p xc3s200-ft256-4
-cm area -pr b -k 4 -c 100 -o vgavga_map.ncd vgavga.ngd vgavga.pcf 
Target Device  : xc3s200
Target Package : ft256
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.36 $
Mapped Date    : Sun Jun 01 01:44:13 2008

Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...

Design Summary
--------------

Design Summary:
Number of errors:      0
Number of warnings:    0
Logic Utilization:
  Number of Slice Flip Flops:          22 out of   3,840    1%
  Number of 4 input LUTs:              19 out of   3,840    1%
Logic Distribution:
  Number of occupied Slices:                           20 out of   1,920    1%
    Number of Slices containing only related logic:      20 out of      20  100%
    Number of Slices containing unrelated logic:          0 out of      20    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number of 4 input LUTs:             36 out of   3,840    1%
  Number used as logic:                 19
  Number used as a route-thru:          17
  Number of bonded IOBs:                8 out of     173    4%
    IOB Flip Flops:                     3
  Number of GCLKs:                     2 out of       8   25%
  Number of DCMs:                      1 out of       4   25%

Total equivalent gate count for design:  7,422
Additional JTAG gate count for IOBs:  384
Peak Memory Usage:  135 MB
Total REAL time to MAP completion:  1 secs 
Total CPU time to MAP completion:   1 secs 

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Mapping completed.
See MAP report file "vgavga_map.mrp" for details.