timing.twr

xilinx fpga 做VGA驱动信号的Verilog原代码,ise版本9.2

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                |  Check  | Worst Case |  Best Case | Timing |   Timing   
                                            |         |    Slack   | Achievable | Errors |    Score   
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | SETUP   |         N/A|     5.355ns|     N/A|          99
                                            | HOLD    |     0.992ns|            |       0|           0
------------------------------------------------------------------------------------------------------


1 constraint not met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.