my_dcm_arwz.ucf

xilinx fpga 做VGA驱动信号的Verilog原代码,ise版本9.2

# Generated by Xilinx Architecture Wizard
# --- UCF Template Only ---
# Cut and paste these attributes into the project's UCF file, if desired
INST DCM_INST CLK_FEEDBACK = 1X;
INST DCM_INST CLKDV_DIVIDE = 2.0;
INST DCM_INST CLKFX_DIVIDE = 4;
INST DCM_INST CLKFX_MULTIPLY = 2;
INST DCM_INST CLKIN_DIVIDE_BY_2 = FALSE;
INST DCM_INST CLKIN_PERIOD = 20.000;
INST DCM_INST CLKOUT_PHASE_SHIFT = NONE;
INST DCM_INST DESKEW_ADJUST = SYSTEM_SYNCHRONOUS;
INST DCM_INST DFS_FREQUENCY_MODE = LOW;
INST DCM_INST DLL_FREQUENCY_MODE = LOW;
INST DCM_INST DUTY_CYCLE_CORRECTION = TRUE;
INST DCM_INST FACTORY_JF = 8080;
INST DCM_INST PHASE_SHIFT = 0;
INST DCM_INST STARTUP_WAIT = FALSE;