vgavga.twr

xilinx fpga 做VGA驱动信号的Verilog原代码,ise版本9.2

--------------------------------------------------------------------------------
Release 9.2i Trace 
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

E:\Program Files\xp\Xilinx92i\bin\nt\trce.exe -ise
E:/Program Files/xp/Xilinx92i/mydesign/vgavga/vgavga.ise -intstyle ise -e 3 -s
4 -xml vgavga vgavga.ncd -o vgavga.twr vgavga.pcf -ucf vgavga.ucf

Design file:              vgavga.ncd
Physical constraint file: vgavga.pcf
Device,package,speed:     xc3s200,ft256,-4 (PRODUCTION 1.39 2007-04-13)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on 
   a 50 Ohm transmission line loading model.  For the details of this model, 
   and for more information on accounting for different loading conditions, 
   please see the device datasheet.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clock
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
key<0>      |    5.628(R)|   -3.149(R)|clk               |   0.000|
key<1>      |    5.446(R)|   -2.853(R)|clk               |   0.000|
------------+------------+------------+------------------+--------+

Clock clock to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
vga_B       |    4.649(R)|clk               |   0.000|
vga_G       |    4.649(R)|clk               |   0.000|
vga_R       |    4.649(R)|clk               |   0.000|
vga_h_sync  |    6.405(R)|clk               |   0.000|
vga_v_sync  |    6.015(R)|clk               |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clock
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clock          |    5.125|         |         |         |
---------------+---------+---------+---------+---------+


Analysis completed Sun Jun 01 01:44:25 2008 
--------------------------------------------------------------------------------

Trace Settings:
-------------------------
Trace Settings 

Peak Memory Usage: 77 MB