vgavga.bld

xilinx fpga 做VGA驱动信号的Verilog原代码,ise版本9.2

Release 9.2i ngdbuild J.36
Copyright (c) 1995-2007 Xilinx, Inc.  All rights reserved.

Command Line: E:\Program Files\xp\Xilinx92i\bin\nt\ngdbuild.exe -ise E:/Program
Files/xp/Xilinx92i/mydesign/vgavga/vgavga.ise -intstyle ise -dd _ngo -nt
timestamp -uc vgavga.ucf -p xc3s200-ft256-4 vgavga.ngc vgavga.ngd

Reading NGO file "E:/Program Files/xp/Xilinx92i/mydesign/vgavga/vgavga.ngc" ...

Applying constraints in "vgavga.ucf" to the design...

Checking timing specifications ...
Checking Partitions ...
Checking expanded design ...
WARNING:NgdBuild:971 - IO attribute 'LOC' on net 'clk' has been applied
   incorrectly. It should be placed on a port net, pad, or a buffer.

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:   1

Total memory usage is 70716 kilobytes

Writing NGD file "vgavga.ngd" ...

Writing NGDBUILD log file "vgavga.bld"...