uart_test.vhd

UART-FPGA完全好用的程序，ISE8.2下打开

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    07:51:12 10/26/2008 
-- Design Name: 
-- Module Name:    uart_test - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
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-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity uart_test is
    Port ( clk : in  STD_LOGIC;
           reset : in  STD_LOGIC;
           btn : in  STD_LOGIC_VECTOR (2 downto 0);
           rx : in  STD_LOGIC;
           tx : out  STD_LOGIC;
           led : out  STD_LOGIC_VECTOR (7 downto 0);
           sseg : out  STD_LOGIC_VECTOR (7 downto 0);
           an : out  STD_LOGIC_VECTOR (3 downto 0));
end uart_test;

architecture arch of uart_test is

	signal tx_full, rx_empty: std_logic;
	signal rec_data, rec_data1: std_logic_vector ( 7 downto 0 ) ;
	signal btn_tick: std_logic;
-- instantiate uart
uart_unit: entity work.uart (str_arch)
		port map(clk=>clk, reset=>reset, rd_uart=>btn_tick,
					wr_uart=>btn_tick, rx=>rx, w_data=>rec_datal,
					r_data=>rec_data, tx=>tx, tx_full=>tx_full, rx_empty=>rx_empty);
--instantiate debounce circuit
btn_db_unit : entity work.debounce (fsmd_arch)
	port map(clk=>clk, reset=>reset , sw=>btn(O),
				db_level=>open, db_tick=>btn_tick);
--incremented data loop back
rec_data1 <= std_logic_vector(unsigned(rec_data)+l);
--led display
led <= rec_data;
an <= "1110";
sseg <= '1' & ( not tx_full ) & "11" & (not rx_empty) & "111";
end arch;