uartb.par

UART-FPGA完全好用的程序，ISE8.2下打开

Release 8.2i par I.31
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

LIANG::  Wed Nov 12 13:51:03 2008

par -w -intstyle ise -ol std -t 1 uartb_map.ncd uartb.ncd uartb.pcf 


Constraints file: uartb.pcf.
Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx.
   "uartb" is an NCD, version 3.1, device xc3s200, package ft256, speed -4

Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".

Device speed data version:  "PRODUCTION 1.38 2006-05-03".


Device Utilization Summary:

   Number of BUFGMUXs                  2 out of 8      25%
   Number of External IOBs            24 out of 173    13%
      Number of LOCed IOBs             0 out of 24      0%

   Number of Slices                  140 out of 1920    7%
      Number of SLICEMs                0 out of 960     0%



Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989871) REAL time: 3 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 3 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 6 secs 

Phase 4.3
Phase 4.3 (Checksum:26259fc) REAL time: 6 secs 

Phase 5.5
Phase 5.5 (Checksum:2faf07b) REAL time: 6 secs 

Phase 6.8
.....
.....
........
......
...
Phase 6.8 (Checksum:9e3097) REAL time: 6 secs 

Phase 7.5
Phase 7.5 (Checksum:42c1d79) REAL time: 6 secs 

Phase 8.18
Phase 8.18 (Checksum:4c4b3f8) REAL time: 7 secs 

Phase 9.5
Phase 9.5 (Checksum:55d4a77) REAL time: 7 secs 

Writing design to file uartb.ncd


Total REAL time to Placer completion: 7 secs 
Total CPU time to Placer completion: 7 secs 

Starting Router

Phase 1: 1018 unrouted;       REAL time: 7 secs 

Phase 2: 928 unrouted;       REAL time: 7 secs 

Phase 3: 351 unrouted;       REAL time: 8 secs 

Phase 4: 351 unrouted; (1543)      REAL time: 8 secs 

Phase 5: 353 unrouted; (0)      REAL time: 8 secs 

Phase 6: 0 unrouted; (0)      REAL time: 8 secs 

Phase 7: 0 unrouted; (0)      REAL time: 8 secs 

WARNING:Route:447 - CLK Net:reset_BUFGP may have excessive skew because 
   78 NON-CLK pins failed to route using a CLK template.

Total REAL time to Router completion: 8 secs 
Total CPU time to Router completion: 8 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |      BUFGMUX3| No   |   78 |  0.041     |  1.052      |
+---------------------+--------------+------+------+------------+-------------+
|         reset_BUFGP |      BUFGMUX1| No   |   88 |  0.001     |  1.012      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.135
   The MAXIMUM PIN DELAY IS:                               5.783
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.820

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
         516         390          71          15          24           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of
                                            |            |            | Levels | Slack      |errors   
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | N/A        | 6.444ns    | 3      | N/A        | N/A     
  _BUFGP                                    |            |            |        |            |         
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net res | N/A        | 3.380ns    | 2      | N/A        | N/A     
  et_BUFGP                                  |            |            |        |            |         
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 11 secs 
Total CPU time to PAR completion: 10 secs 

Peak Memory Usage:  133 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 1
Number of info messages: 1

Writing design to file uartb.ncd



PAR done!