mod_m_counter.vhd

UART-FPGA完全好用的程序，ISE8.2下打开

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-- Company: 
-- Engineer: 
-- 
-- Create Date:    01:53:07 10/19/2008 
-- Design Name: 
-- Module Name:    mod_m_counter - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library ieee;
use ieee.std_logic_1164.all;
use ieee . numeric_std.all;
entity mod_m_counter is
	generic (
		N:integer := 8; -- number of bits
		M:integer := 163 -- mod M(10)
		);
	port(
		clk, reset: in std_logic;
		max_tick: out std_logic;
		q: out std_logic_vector ( N-1 downto 0)
		);
end mod_m_counter ;
architecture arch of mod_m_counter is
	signal r_reg : unsigned ( N-1 downto 0 );
	signal r_next: unsigned ( N-1 downto 0 );
begin
	-- register
	process (clk, reset)
		begin
			if (reset='1') then
				r_reg <= ( others => '0');
			elsif (clk'event and clk='1') then
				r_reg <= r_next;
			end if ;
	end process;
	--next_state logic
	r_next <= ( others => '0') when r_reg=(M-1) else
				r_reg + 1;
	-- output logic
	q <= std_logic_vector(r_reg);
	max_tick <= '1' when r_reg=(M-1) else '0';
end arch;