uartb.syr

UART-FPGA完全好用的程序，ISE8.2下打开

-------------------
 idle  | 00
 start | 01
 data  | 10
 stop  | 11
-------------------
Analyzing FSM <FSM_0> for best encoding.
Optimizing FSM <uart_rx_unit/state_reg> on signal <state_reg[1:2]> with sequential encoding.
-------------------
 State | Encoding
-------------------
 idle  | 00
 start | 01
 data  | 10
 stop  | 11
-------------------
Loading device for application Rf_Device from file '3s200.nph' in environment C:\Xilinx.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# FSMs                                                 : 2
# ROMs                                                 : 4
 4x1-bit ROM                                           : 4
# Adders/Subtractors                                   : 9
 2-bit adder                                           : 4
 3-bit adder                                           : 2
 4-bit adder                                           : 2
 8-bit adder                                           : 1
# Registers                                            : 76
 Flip-Flops                                            : 76
# Latches                                              : 6
 1-bit latch                                           : 2
 2-bit latch                                           : 4
# Comparators                                          : 4
 2-bit comparator equal                                : 4
# Multiplexers                                         : 10
 1-bit 4-to-1 multiplexer                              : 4
 2-bit 4-to-1 multiplexer                              : 4
 8-bit 4-to-1 multiplexer                              : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <uartb> ...

Optimizing unit <uart_rx> ...

Optimizing unit <mod_m_counter> ...

Optimizing unit <uart_tx> ...

Optimizing unit <fifo> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block uartb, actual ratio is 6.
FlipFlop uart_rx_unit/state_reg_FFd1 has been replicated 1 time(s)
FlipFlop uart_tx_unit/state_reg_FFd1 has been replicated 4 time(s)
FlipFlop uart_tx_unit/state_reg_FFd2 has been replicated 2 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 116
 Flip-Flops                                            : 116

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : uartb.ngr
Top Level Output File Name         : uartb
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 24

Cell Usage :
# BELS                             : 228
#      INV                         : 2
#      LUT2                        : 8
#      LUT2_D                      : 2
#      LUT2_L                      : 3
#      LUT3                        : 59
#      LUT3_D                      : 3
#      LUT4                        : 95
#      LUT4_D                      : 8
#      LUT4_L                      : 18
#      MUXF5                       : 30
# FlipFlops/Latches                : 126
#      FDC                         : 41
#      FDCE                        : 72
#      FDP                         : 3
#      LD                          : 10
# Clock Buffers                    : 2
#      BUFGP                       : 2
# IO Buffers                       : 22
#      IBUF                        : 11
#      OBUF                        : 11
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 3s200ft256-4 

 Number of Slices:                     126  out of   1920     6%  
 Number of Slice Flip Flops:           126  out of   3840     3%  
 Number of 4 input LUTs:               198  out of   3840     5%  
 Number of IOs:                         24
 Number of bonded IOBs:                 24  out of    173    13%  
 Number of GCLKs:                        2  out of      8    25%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 116   |
reset                              | BUFGP                  | 10    |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
-----------------------------------+------------------------+-------+
Control Signal                     | Buffer(FF name)        | Load  |
-----------------------------------+------------------------+-------+
reset                              | BUFGP                  | 116   |
-----------------------------------+------------------------+-------+

Timing Summary:
---------------
Speed Grade: -4

   Minimum period: 7.524ns (Maximum Frequency: 132.908MHz)
   Minimum input arrival time before clock: 5.048ns
   Maximum output required time after clock: 9.928ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 7.524ns (frequency: 132.908MHz)
  Total number of paths / destination ports: 1730 / 123
-------------------------------------------------------------------------
Delay:               7.524ns (Levels of Logic = 4)
  Source:            baud_gen_unit/r_reg_3 (FF)
  Destination:       uart_rx_unit/s_reg_2 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: baud_gen_unit/r_reg_3 to uart_rx_unit/s_reg_2
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDC:C->Q              3   0.720   1.246  baud_gen_unit/r_reg_3 (baud_gen_unit/r_reg_3)
     LUT4_D:I0->O          5   0.551   0.947  baud_gen_unit/_cmp_eq000022 (baud_gen_unit/_cmp_eq0000_map563)
     LUT4:I3->O            4   0.551   0.943  baud_gen_unit/_cmp_eq000023_1 (baud_gen_unit/_cmp_eq000023)
     LUT4:I3->O            7   0.551   1.261  uart_rx_unit/rx_done_tick (rx_done_tick)
     LUT4:I1->O            1   0.551   0.000  uart_rx_unit/_mux0015<1>37 (uart_rx_unit/_mux0015<1>)
     FDC:D                     0.203          uart_rx_unit/s_reg_2
    ----------------------------------------
    Total                      7.524ns (3.127ns logic, 4.397ns route)
                                       (41.6% logic, 58.4% route)

=========================================================================
Timing constraint: Default period analysis for Clock 'reset'
  Clock period: 5.233ns (frequency: 191.095MHz)
  Total number of paths / destination ports: 36 / 10
-------------------------------------------------------------------------
Delay:               5.233ns (Levels of Logic = 3)
  Source:            fifo_rx_unit/r_ptr_reg_0 (LATCH)
  Destination:       fifo_rx_unit/full_reg (LATCH)
  Source Clock:      reset falling
  Destination Clock: reset falling

  Data Path: fifo_rx_unit/r_ptr_reg_0 to fifo_rx_unit/full_reg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q              22   0.633   1.939  fifo_rx_unit/r_ptr_reg_0 (fifo_rx_unit/r_ptr_reg_0)
     LUT4:I0->O            1   0.551   0.996  fifo_rx_unit/Mcompar__cmp_eq0001_AEB1 (fifo_rx_unit/_cmp_eq0001)
     LUT4:I1->O            1   0.551   0.000  fifo_rx_unit/_mux0005_G (N684)
     MUXF5:I1->O           1   0.360   0.000  fifo_rx_unit/_mux0005 (fifo_rx_unit/_mux0005)
     LD:D                      0.203          fifo_rx_unit/full_reg
    ----------------------------------------
    Total                      5.233ns (2.298ns logic, 2.935ns route)
                                       (43.9% logic, 56.1% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 78 / 72
-------------------------------------------------------------------------
Offset:              5.048ns (Levels of Logic = 4)
  Source:            rx (PAD)
  Destination:       uart_rx_unit/s_reg_0 (FF)
  Destination Clock: clk rising

  Data Path: rx to uart_rx_unit/s_reg_0
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O             8   0.821   1.422  rx_IBUF (rx_IBUF)
     LUT4:I0->O            1   0.551   1.140  uart_rx_unit/_mux0015<3>37_SW1 (N640)
     LUT3:I0->O            1   0.551   0.000  uart_rx_unit/_mux0015<3>38_G (N694)
     MUXF5:I1->O           1   0.360   0.000  uart_rx_unit/_mux0015<3>38 (uart_rx_unit/_mux0015<3>)
     FDC:D                     0.203          uart_rx_unit/s_reg_0
    ----------------------------------------
    Total                      5.048ns (2.486ns logic, 2.562ns route)
                                       (49.2% logic, 50.8% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'reset'
  Total number of paths / destination ports: 13 / 10
-------------------------------------------------------------------------
Offset:              3.444ns (Levels of Logic = 3)
  Source:            wr_uart (PAD)
  Destination:       fifo_tx_unit/full_reg (LATCH)
  Destination Clock: reset falling

  Data Path: wr_uart to fifo_tx_unit/full_reg
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O            13   0.821   1.509  wr_uart_IBUF (wr_uart_IBUF)
     LUT4:I0->O            1   0.551   0.000  fifo_tx_unit/_mux0005_F (N685)
     MUXF5:I0->O           1   0.360   0.000  fifo_tx_unit/_mux0005 (fifo_tx_unit/_mux0005)
     LD:D                      0.203          fifo_tx_unit/full_reg
    ----------------------------------------
    Total                      3.444ns (1.935ns logic, 1.509ns route)
                                       (56.2% logic, 43.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 34 / 10
-------------------------------------------------------------------------
Offset:              9.072ns (Levels of Logic = 3)
  Source:            fifo_rx_unit/array_reg_0_7 (FF)
  Destination:       r_data<7> (PAD)
  Source Clock:      clk rising

  Data Path: fifo_rx_unit/array_reg_0_7 to r_data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FDCE:C->Q             1   0.720   0.996  fifo_rx_unit/array_reg_0_7 (fifo_rx_unit/array_reg_0_7)
     LUT3:I1->O            1   0.551   0.000  fifo_rx_unit/r_ptr_reg<0>15 (fifo_rx_unit/N17)
     MUXF5:I0->O           1   0.360   0.801  fifo_rx_unit/Mmux_r_data_f5_6 (r_data_7_OBUF)
     OBUF:I->O                 5.644          r_data_7_OBUF (r_data<7>)
    ----------------------------------------
    Total                      9.072ns (7.275ns logic, 1.797ns route)
                                       (80.2% logic, 19.8% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'reset'
  Total number of paths / destination ports: 25 / 9
-------------------------------------------------------------------------
Offset:              9.928ns (Levels of Logic = 3)
  Source:            fifo_rx_unit/r_ptr_reg_0 (LATCH)
  Destination:       r_data<7> (PAD)
  Source Clock:      reset falling

  Data Path: fifo_rx_unit/r_ptr_reg_0 to r_data<7>
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     LD:G->Q              22   0.633   1.939  fifo_rx_unit/r_ptr_reg_0 (fifo_rx_unit/r_ptr_reg_0)
     LUT3:I0->O            1   0.551   0.000  fifo_rx_unit/r_ptr_reg<0>14 (fifo_rx_unit/N16)
     MUXF5:I1->O           1   0.360   0.801  fifo_rx_unit/Mmux_r_data_f5_6 (r_data_7_OBUF)
     OBUF:I->O                 5.644          r_data_7_OBUF (r_data<7>)
    ----------------------------------------
    Total                      9.928ns (7.188ns logic, 2.740ns route)
                                       (72.4% logic, 27.6% route)

=========================================================================
CPU : 19.41 / 19.97 s | Elapsed : 19.00 / 19.00 s
 
--> 

Total memory usage is 134768 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    6 (   0 filtered)
Number of infos    :    1 (   0 filtered)