uartb.syr

UART-FPGA完全好用的程序，ISE8.2下打开

Release 8.2i - xst I.31
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: uartb.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "uartb.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "uartb"
Output Format                      : NGC
Target Device                      : xc3s200-4-ft256

---- Source Options
Top Module Name                    : uartb
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Multiplier Style                   : auto
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 8
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : uartb.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Yes
use_sync_set                       : Yes
use_sync_reset                     : Yes

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "D:/uart/uart/mod_m_counter.vhd" in Library work.
Entity <mod_m_counter> compiled.
Entity <mod_m_counter> (Architecture <arch>) compiled.
Compiling vhdl file "D:/uart/uart/uart_rx.vhd" in Library work.
Entity <uart_rx> compiled.
Entity <uart_rx> (Architecture <arch>) compiled.
Compiling vhdl file "D:/uart/uart/fifo.vhd" in Library work.
Entity <fifo> compiled.
Entity <fifo> (Architecture <arch>) compiled.
Compiling vhdl file "D:/uart/uart/uart-tx.vhd" in Library work.
Entity <uart_tx> compiled.
Entity <uart_tx> (Architecture <arch>) compiled.
Compiling vhdl file "D:/uart/uart/uart.vhd" in Library work.
Entity <uartb> compiled.
Entity <uartb> (Architecture <str_arch>) compiled.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <uartb> in library <work> (architecture <str_arch>) with generics.
	DBIT = 8
	DVSR = 163
	DVSR_BIT = 8
	FIFO_W = 2
	SB_TICK = 16

Analyzing hierarchy for entity <mod_m_counter> in library <work> (architecture <arch>) with generics.
	M = 163
	N = 8

Analyzing hierarchy for entity <uart_rx> in library <work> (architecture <arch>) with generics.
	DBIT = 8
	SB_TICK = 16

Analyzing hierarchy for entity <fifo> in library <work> (architecture <arch>) with generics.
	B = 8
	W = 2

Analyzing hierarchy for entity <uart_tx> in library <work> (architecture <arch>) with generics.
	DBIT = 8
	SB_TICK = 16

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing generic Entity <uartb> in library <work> (Architecture <str_arch>).
	DBIT = 8
	SB_TICK = 16
	DVSR = 163
	DVSR_BIT = 8
	FIFO_W = 2
WARNING:Xst:753 - "D:/uart/uart/uart.vhd" line 72: Unconnected output port 'q' of component 'mod_m_counter'.
WARNING:Xst:753 - "D:/uart/uart/uart.vhd" line 79: Unconnected output port 'full' of component 'fifo'.
Entity <uartb> analyzed. Unit <uartb> generated.

Analyzing generic Entity <mod_m_counter> in library <work> (Architecture <arch>).
	N = 8
	M = 163
Entity <mod_m_counter> analyzed. Unit <mod_m_counter> generated.

Analyzing generic Entity <uart_rx> in library <work> (Architecture <arch>).
	DBIT = 8
	SB_TICK = 16
Entity <uart_rx> analyzed. Unit <uart_rx> generated.

Analyzing generic Entity <fifo> in library <work> (Architecture <arch>).
	B = 8
	W = 2
WARNING:Xst:819 - "D:/uart/uart/fifo.vhd" line 68: The following signals are missing in the process sensitivity list:
   w_ptr_next, r_ptr_next, full_next.
Entity <fifo> analyzed. Unit <fifo> generated.

Analyzing generic Entity <uart_tx> in library <work> (Architecture <arch>).
	SB_TICK = 16
	DBIT = 8
Entity <uart_tx> analyzed. Unit <uart_tx> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <mod_m_counter>.
    Related source file is "D:/uart/uart/mod_m_counter.vhd".
    Found 8-bit adder for signal <$addsub0000> created at line 48.
    Found 8-bit register for signal <r_reg>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   1 Adder/Subtractor(s).
Unit <mod_m_counter> synthesized.


Synthesizing Unit <uart_rx>.
    Related source file is "D:/uart/uart/uart_rx.vhd".
    Found finite state machine <FSM_0> for signal <state_reg>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 12                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit adder for signal <$addsub0000> created at line 96.
    Found 4-bit adder for signal <$share0000> created at line 72.
    Found 8-bit register for signal <b_reg>.
    Found 3-bit register for signal <n_reg>.
    Found 4-bit register for signal <s_reg>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  15 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <uart_rx> synthesized.


Synthesizing Unit <fifo>.
    Related source file is "D:/uart/uart/fifo.vhd".
WARNING:Xst:737 - Found 2-bit latch for signal <w_ptr_reg>.
WARNING:Xst:737 - Found 2-bit latch for signal <r_ptr_reg>.
WARNING:Xst:737 - Found 1-bit latch for signal <full_reg>.
    Found 4x1-bit ROM for signal <$mux0009> created at line 96.
    Found 4x1-bit ROM for signal <$mux0010> created at line 104.
    Found 8-bit 4-to-1 multiplexer for signal <r_data>.
    Found 2-bit adder for signal <$add0000> created at line 84.
    Found 2-bit adder for signal <$add0001> created at line 83.
    Found 2-bit comparator equal for signal <$cmp_eq0000> created at line 99.
    Found 2-bit comparator equal for signal <$cmp_eq0001> created at line 107.
    Found 2-bit 4-to-1 multiplexer for signal <$mux0002> created at line 93.
    Found 2-bit 4-to-1 multiplexer for signal <$mux0003> created at line 93.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0004> created at line 93.
    Found 1-bit 4-to-1 multiplexer for signal <$mux0005> created at line 93.
    Found 32-bit register for signal <array_reg>.
    Found 1-bit register for signal <empty_reg>.
    Summary:
	inferred   2 ROM(s).
	inferred  33 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
	inferred   2 Comparator(s).
	inferred  14 Multiplexer(s).
Unit <fifo> synthesized.


Synthesizing Unit <uart_tx>.
    Related source file is "D:/uart/uart/uart-tx.vhd".
    Found finite state machine <FSM_1> for signal <state_reg>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 12                                             |
    | Inputs             | 4                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | automatic                                      |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit adder for signal <$add0000> created at line 87.
    Found 3-bit adder for signal <$addsub0000> created at line 99.
    Found 8-bit register for signal <b_reg>.
    Found 3-bit register for signal <n_reg>.
    Found 4-bit register for signal <s_reg>.
    Found 1-bit register for signal <tx_reg>.
    Summary:
	inferred   1 Finite State Machine(s).
	inferred  16 D-type flip-flop(s).
	inferred   2 Adder/Subtractor(s).
Unit <uart_tx> synthesized.


Synthesizing Unit <uartb>.
    Related source file is "D:/uart/uart/uart.vhd".
Unit <uartb> synthesized.

INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.

=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 4
 4x1-bit ROM                                           : 4
# Adders/Subtractors                                   : 9
 2-bit adder                                           : 4
 3-bit adder                                           : 2
 4-bit adder                                           : 2
 8-bit adder                                           : 1
# Registers                                            : 18
 1-bit register                                        : 3
 3-bit register                                        : 2
 4-bit register                                        : 2
 8-bit register                                        : 11
# Latches                                              : 6
 1-bit latch                                           : 2
 2-bit latch                                           : 4
# Comparators                                          : 4
 2-bit comparator equal                                : 4
# Multiplexers                                         : 10
 1-bit 4-to-1 multiplexer                              : 4
 2-bit 4-to-1 multiplexer                              : 4
 8-bit 4-to-1 multiplexer                              : 2

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Analyzing FSM <FSM_1> for best encoding.
Optimizing FSM <uart_tx_unit/state_reg> on signal <state_reg[1:2]> with sequential encoding.
-------------------
 State | Encoding