uartb.twr

UART-FPGA完全好用的程序，ISE8.2下打开

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Release 8.2i Trace 
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

C:\Xilinx\bin\nt\trce.exe -ise D:/uart/uart/uart.ise -intstyle ise -e 3 -l 3 -s
4 -xml uartb uartb.ncd -o uartb.twr uartb.pcf

Design file:              uartb.ncd
Physical constraint file: uartb.pcf
Device,speed:             xc3s200,-4 (PRODUCTION 1.38 2006-05-03)
Report level:             error report

Environment Variable      Effect 
--------------------      ------ 
NONE                      No environment variables were set
--------------------------------------------------------------------------------

INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths 
   option. All paths that are not constrained will be reported in the 
   unconstrained paths section(s) of the report.



Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)

Setup/Hold to clock clk
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
rd_uart     |    3.830(R)|   -1.498(R)|clk_BUFGP         |   0.000|
rx          |    4.137(R)|   -0.201(R)|clk_BUFGP         |   0.000|
w_data<0>   |    3.018(R)|    1.153(R)|clk_BUFGP         |   0.000|
w_data<1>   |    3.019(R)|    1.192(R)|clk_BUFGP         |   0.000|
w_data<2>   |    3.018(R)|    0.855(R)|clk_BUFGP         |   0.000|
w_data<3>   |    3.018(R)|    1.214(R)|clk_BUFGP         |   0.000|
w_data<4>   |    3.018(R)|    1.137(R)|clk_BUFGP         |   0.000|
w_data<5>   |    3.018(R)|    1.176(R)|clk_BUFGP         |   0.000|
w_data<6>   |    3.019(R)|    0.771(R)|clk_BUFGP         |   0.000|
w_data<7>   |    3.018(R)|    0.757(R)|clk_BUFGP         |   0.000|
wr_uart     |    4.643(R)|   -0.959(R)|clk_BUFGP         |   0.000|
------------+------------+------------+------------------+--------+

Setup/Hold to clock reset
------------+------------+------------+------------------+--------+
            |  Setup to  |  Hold to   |                  | Clock  |
Source      | clk (edge) | clk (edge) |Internal Clock(s) | Phase  |
------------+------------+------------+------------------+--------+
rd_uart     |    2.783(F)|   -0.276(F)|reset_BUFGP       |   0.000|
wr_uart     |    2.390(F)|    0.364(F)|reset_BUFGP       |   0.000|
------------+------------+------------+------------------+--------+

Clock clk to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
r_data<0>   |   10.946(R)|clk_BUFGP         |   0.000|
r_data<1>   |   11.971(R)|clk_BUFGP         |   0.000|
r_data<2>   |   11.624(R)|clk_BUFGP         |   0.000|
r_data<3>   |   12.315(R)|clk_BUFGP         |   0.000|
r_data<4>   |   11.173(R)|clk_BUFGP         |   0.000|
r_data<5>   |   11.771(R)|clk_BUFGP         |   0.000|
r_data<6>   |   11.377(R)|clk_BUFGP         |   0.000|
r_data<7>   |   11.978(R)|clk_BUFGP         |   0.000|
rx_empty    |   10.105(R)|clk_BUFGP         |   0.000|
tx          |    7.359(R)|clk_BUFGP         |   0.000|
------------+------------+------------------+--------+

Clock reset to Pad
------------+------------+------------------+--------+
            | clk (edge) |                  | Clock  |
Destination |   to PAD   |Internal Clock(s) | Phase  |
------------+------------+------------------+--------+
r_data<0>   |   11.030(F)|reset_BUFGP       |   0.000|
r_data<1>   |   11.398(F)|reset_BUFGP       |   0.000|
r_data<2>   |   11.983(F)|reset_BUFGP       |   0.000|
r_data<3>   |   11.215(F)|reset_BUFGP       |   0.000|
r_data<4>   |   11.328(F)|reset_BUFGP       |   0.000|
r_data<5>   |   11.670(F)|reset_BUFGP       |   0.000|
r_data<6>   |   11.548(F)|reset_BUFGP       |   0.000|
r_data<7>   |   11.649(F)|reset_BUFGP       |   0.000|
tx_full     |    9.461(F)|reset_BUFGP       |   0.000|
------------+------------+------------------+--------+

Clock to Setup on destination clock clk
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |    6.444|         |         |         |
reset          |         |    7.045|         |         |
---------------+---------+---------+---------+---------+

Clock to Setup on destination clock reset
---------------+---------+---------+---------+---------+
               | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
Source Clock   |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
---------------+---------+---------+---------+---------+
clk            |         |         |    7.669|         |
reset          |         |         |         |    3.380|
---------------+---------+---------+---------+---------+


Analysis completed Wed Nov 12 13:51:20 2008
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Trace Settings:
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Trace Settings 

Peak Memory Usage: 105 MB