uartb_map.mrp

UART-FPGA完全好用的程序，ISE8.2下打开

Release 8.2i Map I.31
Xilinx Mapping Report File for Design 'uartb'

Design Information
------------------
Command Line   : C:\Xilinx\bin\nt\map.exe -ise D:/uart/uart/uart.ise -intstyle
ise -p xc3s200-ft256-4 -cm area -pr b -k 4 -c 100 -o uartb_map.ncd uartb.ngd
uartb.pcf 
Target Device  : xc3s200
Target Package : ft256
Target Speed   : -4
Mapper Version : spartan3 -- $Revision: 1.34.32.1 $
Mapped Date    : Wed Nov 12 13:50:57 2008

Design Summary
--------------
Number of errors:      0
Number of warnings:    3
Logic Utilization:
  Total Number Slice Registers:       116 out of   3,840    3%
    Number used as Flip Flops:                   106
    Number used as Latches:                       10
  Number of 4 input LUTs:             196 out of   3,840    5%
Logic Distribution:
  Number of occupied Slices:                          140 out of   1,920    7%
    Number of Slices containing only related logic:     140 out of     140  100%
    Number of Slices containing unrelated logic:          0 out of     140    0%
      *See NOTES below for an explanation of the effects of unrelated logic
Total Number 4 input LUTs:            198 out of   3,840    5%
  Number used as logic:                196
  Number used as a route-thru:           2
  Number of bonded IOBs:               24 out of     173   13%
    IOB Flip Flops:                    10
  Number of GCLKs:                     2 out of       8   25%

Total equivalent gate count for design:  2,250
Additional JTAG gate count for IOBs:  1,152
Peak Memory Usage:  137 MB

NOTES:

   Related logic is defined as being logic that shares connectivity - e.g. two
   LUTs are "related" if they share common inputs.  When assembling slices,
   Map gives priority to combine logic that is related.  Doing so results in
   the best timing performance.

   Unrelated logic shares no connectivity.  Map will only begin packing
   unrelated logic into a slice once 99% of the slices are occupied through
   related logic packing.

   Note that once logic distribution reaches the 99% level through related
   logic packing, this does not mean the device is completely utilized.
   Unrelated logic packing will then begin, continuing until all usable LUTs
   and FFs are occupied.  Depending on your timing budget, increased levels of
   unrelated logic packing may adversely affect the overall timing performance
   of your design.

Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information

Section 1 - Errors
------------------

Section 2 - Warnings
--------------------
WARNING:LIT:243 - Logical network N697 has no load.
WARNING:LIT:395 - The above warning message base_net_load_rule is repeated 1
   more times for the following (max. 5 shown):
   N698
   To see the details of these warning messages, please use the -detail switch.
WARNING:LIT:175 - Clock buffer is designated to drive clock loads. BUFGMUX
   symbol "physical_group_reset_BUFGP/reset_BUFGP/BUFG" (output
   signal=reset_BUFGP) has a mix of clock and non-clock loads. Some of the
   non-clock loads are (maximum of 5 listed):
   Pin CLR of uart_rx_unit/b_reg_0
   Pin CLR of uart_rx_unit/b_reg_1
   Pin CLR of uart_rx_unit/b_reg_2
   Pin CLR of uart_rx_unit/b_reg_3
   Pin CLR of uart_rx_unit/b_reg_4

Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:MapLib:535 - The following Virtex BUFG(s) is/are being retargetted to
   Virtex2 BUFGMUX(s) with input tied to I0 and Select pin tied to constant 0:
   BUFGP symbol "clk_BUFGP" (output signal=clk_BUFGP),
   BUFGP symbol "reset_BUFGP" (output signal=reset_BUFGP)
INFO:LIT:244 - All of the single ended outputs in this design are using slew
   rate limited output drivers. The delay on speed critical single ended outputs
   can be dramatically reduced by designating them as fast outputs in the
   schematic.

Section 4 - Removed Logic Summary
---------------------------------
   2 block(s) removed
   2 signal(s) removed

Section 5 - Removed Logic
-------------------------

The trimmed logic report below shows the logic removed from your design due to
sourceless or loadless signals, and VCC or ground connections.  If the removal
of a signal or symbol results in the subsequent removal of an additional signal
or symbol, the message explaining that second removal will be indented.  This
indentation will be repeated as a chain of related logic is removed.

To quickly locate the original cause for the removal of a chain of logic, look
above the place where that logic is listed in the trimming report, then locate
the lines that are least indented (begin at the leftmost edge).

The signal "N697" is loadless and has been removed.
 Loadless block "XST_VCC" (ONE) removed.
The signal "N698" is loadless and has been removed.
 Loadless block "XST_GND" (ZERO) removed.

To enable printing of redundant blocks removed and signals merged, set the
detailed map report option and rerun map.

Section 6 - IOB Properties
--------------------------

+------------------------------------------------------------------------------------------------------------------------+
| IOB Name                           | Type    | Direction | IO Standard | Drive    | Slew | Reg (s)  | Resistor | IOB   |
|                                    |         |           |             | Strength | Rate |          |          | Delay |
+------------------------------------------------------------------------------------------------------------------------+
| clk                                | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| r_data<0>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| r_data<1>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| r_data<2>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| r_data<3>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| r_data<4>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| r_data<5>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| r_data<6>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| r_data<7>                          | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| rd_uart                            | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| reset                              | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
| rx                                 | IOB     | INPUT     | LVCMOS25    |          |      | INFF1    |          | IFD   |
| rx_empty                           | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| tx                                 | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW | OFF1     |          |       |
| tx_full                            | IOB     | OUTPUT    | LVCMOS25    | 12       | SLOW |          |          |       |
| w_data<0>                          | IOB     | INPUT     | LVCMOS25    |          |      | INFF1    |          | IFD   |
| w_data<1>                          | IOB     | INPUT     | LVCMOS25    |          |      | INFF1    |          | IFD   |
| w_data<2>                          | IOB     | INPUT     | LVCMOS25    |          |      | INFF1    |          | IFD   |
| w_data<3>                          | IOB     | INPUT     | LVCMOS25    |          |      | INFF1    |          | IFD   |
| w_data<4>                          | IOB     | INPUT     | LVCMOS25    |          |      | INFF1    |          | IFD   |
| w_data<5>                          | IOB     | INPUT     | LVCMOS25    |          |      | INFF1    |          | IFD   |
| w_data<6>                          | IOB     | INPUT     | LVCMOS25    |          |      | INFF1    |          | IFD   |
| w_data<7>                          | IOB     | INPUT     | LVCMOS25    |          |      | INFF1    |          | IFD   |
| wr_uart                            | IOB     | INPUT     | LVCMOS25    |          |      |          |          |       |
+------------------------------------------------------------------------------------------------------------------------+

Section 7 - RPMs
----------------

Section 8 - Guide Report
------------------------
Guide not run on this design.

Section 9 - Area Group and Partition Summary
--------------------------------------------

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Area Group Information
----------------------

  No area groups were found in this design.

----------------------

Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.

Section 11 - Timing Report
--------------------------
This design was not run using timing mode.

Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings