c60.rpt

lcd扫描

  31     26    B     OUTPUT      t        0      0   0    0    5    0    0  out


Code:

s = Synthesized pin or logic cell
t = Turbo logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell


Device-Specific Information:                               e:\cpld工程\c60.rpt
c60

** LOGIC CELL INTERCONNECTIONS **

Logic Array Block 'B':

                         Logic cells placed in LAB 'B'
        +--------------- LC22 c0
        | +------------- LC23 c1
        | | +----------- LC21 c2
        | | | +--------- LC18 c3
        | | | | +------- LC17 c4
        | | | | | +----- LC24 c5
        | | | | | | +--- LC19 c6
        | | | | | | | +- LC26 out
        | | | | | | | | 
        | | | | | | | |   Other LABs fed by signals
        | | | | | | | |   that feed LAB 'B'
LC      | | | | | | | | | A B |     Logic cells that feed LAB 'B':
LC22 -> * * * * * * * * | - * | <-- c0
LC23 -> * * * * * * * * | - * | <-- c1
LC21 -> - - * * * * - - | - * | <-- c2
LC18 -> * * * * * * * * | - * | <-- c3
LC17 -> * * * * * * * * | - * | <-- c4
LC24 -> * * * * * * * * | - * | <-- c5
LC19 -> - - - - - - * - | - * | <-- c6

Pin
43   -> - - - - - - - - | - - | <-- clk
1    -> - - - - - - - - | - - | <-- clr
4    -> * * * * * * - - | - * | <-- en


* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).


Device-Specific Information:                               e:\cpld工程\c60.rpt
c60

** EQUATIONS **

clk      : INPUT;
clr      : INPUT;
en       : INPUT;

-- Node name is 'c0' = '|74161:1|p74161:sub|QA' 
-- Equation name is 'c0', type is output 
 c0      = TFFE( _EQ001, GLOBAL( clk), GLOBAL( clr),  VCC,  VCC);
  _EQ001 =  c0 &  c1 &  c3 &  c4 &  c5
         #  en;

-- Node name is 'c1' = '|74161:1|p74161:sub|QB' 
-- Equation name is 'c1', type is output 
 c1      = TFFE( _EQ002, GLOBAL( clk), GLOBAL( clr),  VCC,  VCC);
  _EQ002 =  c0 &  c1 &  c3 &  c4 &  c5
         #  c0 &  en;

-- Node name is 'c2' = '|74161:1|p74161:sub|QC' 
-- Equation name is 'c2', type is output 
 c2      = TFFE( _EQ003, GLOBAL( clk), GLOBAL( clr),  VCC,  VCC);
  _EQ003 =  c0 &  c1 &  c2 &  c3 &  c4 &  c5
         #  c0 &  c1 & !c2 & !c5 &  en
         #  c0 &  c1 & !c2 & !c4 &  en
         #  c0 &  c1 & !c2 & !c3 &  en
         #  c0 &  c1 &  c2 &  en;

-- Node name is 'c3' = '|74161:1|p74161:sub|QD' 
-- Equation name is 'c3', type is output 
 c3      = TFFE( _EQ004, GLOBAL( clk), GLOBAL( clr),  VCC,  VCC);
  _EQ004 =  c0 &  c1 &  c3 &  c4 &  c5
         #  c0 &  c1 &  c2 &  en;

-- Node name is 'c4' = '|74161:2|p74161:sub|QA' 
-- Equation name is 'c4', type is output 
 c4      = TFFE( _EQ005, GLOBAL( clk), GLOBAL( clr),  VCC,  VCC);
  _EQ005 =  c0 &  c1 &  c2 &  c3 &  en
         #  c0 &  c1 &  c3 &  c4 &  c5;

-- Node name is 'c5' = '|74161:2|p74161:sub|QB' 
-- Equation name is 'c5', type is output 
 c5      = TFFE( _EQ006, GLOBAL( clk), GLOBAL( clr),  VCC,  VCC);
  _EQ006 =  c0 &  c1 &  c2 &  c3 &  c4 & !c5 &  en
         #  c0 &  c1 &  c3 &  c4 &  c5;

-- Node name is 'c6' = '|74161:2|p74161:sub|QC' 
-- Equation name is 'c6', type is output 
 c6      = TFFE( _EQ007, GLOBAL( clk), GLOBAL( clr),  VCC,  VCC);
  _EQ007 =  c0 &  c1 &  c3 &  c4 &  c5 &  c6;

-- Node name is 'out' 
-- Equation name is 'out', location is LC026, type is output.
 out     = LCELL( _EQ008 $  VCC);
  _EQ008 =  c0 &  c1 &  c3 &  c4 &  c5;



--     Shareable expanders that are duplicated in multiple LABs:
--     (none)




Project Information                                        e:\cpld工程\c60.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Standard

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'MAX7000S' family

      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      PARALLEL_EXPANDERS                  = off
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SOFT_BUFFER_INSERTION               = on
      SUBFACTOR_EXTRACTION                = on
      TURBO_BIT                           = on
      XOR_SYNTHESIS                       = on
      IGNORE_SOFT_BUFFERS                 = off
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      One-Hot State Machine Encoding      = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:00
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:01
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 3,793K