📄 clk60.rpt
字号:
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\cpld1\clk60.rpt
clk60
** LOGIC CELL INTERCONNECTIONS **
Logic Array Block 'B':
Logic cells placed in LAB 'B'
+------------------------- LC21 m0
| +----------------------- LC19 m1
| | +--------------------- LC23 m2
| | | +------------------- LC18 m3
| | | | +----------------- LC17 m4
| | | | | +--------------- LC22 m5
| | | | | | +------------- LC29 m6
| | | | | | | +----------- LC27 s1
| | | | | | | | +--------- LC24 s2
| | | | | | | | | +------- LC26 s3
| | | | | | | | | | +----- LC28 s4
| | | | | | | | | | | +--- LC30 s5
| | | | | | | | | | | | +- LC31 s6
| | | | | | | | | | | | |
| | | | | | | | | | | | | Other LABs fed by signals
| | | | | | | | | | | | | that feed LAB 'B'
LC | | | | | | | | | | | | | | A B | Logic cells that feed LAB 'B':
LC21 -> * * * * * * * - - - - - - | * * | <-- m0
LC19 -> * * * * * * * - - - - - - | * * | <-- m1
LC23 -> - - * * * * - - - - - - - | - * | <-- m2
LC18 -> * * * * * * * - - - - - - | * * | <-- m3
LC17 -> * * * * * * * - - - - - - | * * | <-- m4
LC22 -> * * * * * * * - - - - - - | * * | <-- m5
LC29 -> - - - - - - * - - - - - - | - * | <-- m6
LC27 -> * * * * * * - * * * * * * | - * | <-- s1
LC24 -> - - - - - - - - * * * * - | - * | <-- s2
LC26 -> * * * * * * - - * * * * * | - * | <-- s3
LC28 -> * * * * * * - - * * * * * | - * | <-- s4
LC30 -> * * * * * * - - * * * * * | - * | <-- s5
LC31 -> - - - - - - - - - - - - * | - * | <-- s6
Pin
43 -> - - - - - - - - - - - - - | - - | <-- clk
1 -> - - - - - - - - - - - - - | - - | <-- clr
LC2 -> * * * * * * - * * * * * * | - * | <-- s0
* = The logic cell or pin is an input to the logic cell (or LAB) through the PIA.
- = The logic cell or pin is not an input to the logic cell (or LAB).
Device-Specific Information: e:\cpld1\clk60.rpt
clk60
** EQUATIONS **
clk : INPUT;
clr : INPUT;
-- Node name is 'h1' = '|c24:14|74161:1|p74161:sub|QA'
-- Equation name is 'h1', type is output
h1 = TFFE( _EQ001, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ001 = m0 & m1 & m3 & m4 & m5
# h1 & h2 & h3 & h5;
-- Node name is 'h2' = '|c24:14|74161:1|p74161:sub|QB'
-- Equation name is 'h2', type is output
h2 = TFFE( _EQ002, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ002 = h1 & m0 & m1 & m3 & m4 & m5
# h1 & h2 & h3 & h5;
-- Node name is 'h3' = '|c24:14|74161:1|p74161:sub|QC'
-- Equation name is 'h3', type is output
h3 = TFFE( _EQ003, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ003 = h1 & h2 & m0 & m1 & m3 & m4 & m5
# h1 & h2 & h3 & h5;
-- Node name is 'h4' = '|c24:14|74161:1|p74161:sub|QD'
-- Equation name is 'h4', type is output
h4 = TFFE( _EQ004, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ004 = h1 & h2 & h3 & !h4 & !h5 & m0 & m1 & m3 & m4 & m5
# h1 & h2 & h3 & h4 & m0 & m1 & m3 & m4 & m5
# h1 & h2 & h3 & h4 & h5;
-- Node name is 'h5' = '|c24:14|74161:2|p74161:sub|QA'
-- Equation name is 'h5', type is output
h5 = DFFE( _EQ005 $ !h1, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ005 = h1 & h2 & h3 & h4 & !h5 & m0 & m1 & m3 & m4 & m5
# h1 & !h2 & h5
# h1 & !h3 & h5
# !h1 & !h5;
-- Node name is 'm0' = '|c60:16|74161:1|p74161:sub|QA'
-- Equation name is 'm0', type is output
m0 = TFFE( _EQ006, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ006 = s0 & s1 & s3 & s4 & s5
# m0 & m1 & m3 & m4 & m5;
-- Node name is 'm1' = '|c60:16|74161:1|p74161:sub|QB'
-- Equation name is 'm1', type is output
m1 = TFFE( _EQ007, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ007 = m0 & s0 & s1 & s3 & s4 & s5
# m0 & m1 & m3 & m4 & m5;
-- Node name is 'm2' = '|c60:16|74161:1|p74161:sub|QC'
-- Equation name is 'm2', type is output
m2 = TFFE( _EQ008, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ008 = m0 & m1 & !m2 & !m3 & s0 & s1 & s3 & s4 & s5
# m0 & m1 & !m2 & !m4 & s0 & s1 & s3 & s4 & s5
# m0 & m1 & !m2 & !m5 & s0 & s1 & s3 & s4 & s5
# m0 & m1 & m2 & s0 & s1 & s3 & s4 & s5
# m0 & m1 & m2 & m3 & m4 & m5;
-- Node name is 'm3' = '|c60:16|74161:1|p74161:sub|QD'
-- Equation name is 'm3', type is output
m3 = TFFE( _EQ009, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ009 = m0 & m1 & m2 & s0 & s1 & s3 & s4 & s5
# m0 & m1 & m3 & m4 & m5;
-- Node name is 'm4' = '|c60:16|74161:2|p74161:sub|QA'
-- Equation name is 'm4', type is output
m4 = TFFE( _EQ010, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ010 = m0 & m1 & m2 & m3 & s0 & s1 & s3 & s4 & s5
# m0 & m1 & m3 & m4 & m5;
-- Node name is 'm5' = '|c60:16|74161:2|p74161:sub|QB'
-- Equation name is 'm5', type is output
m5 = TFFE( _EQ011, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ011 = m0 & m1 & m2 & m3 & m4 & !m5 & s0 & s1 & s3 & s4 & s5
# m0 & m1 & m3 & m4 & m5;
-- Node name is 'm6' = '|c60:16|74161:2|p74161:sub|QC'
-- Equation name is 'm6', type is output
m6 = TFFE( _EQ012, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ012 = m0 & m1 & m3 & m4 & m5 & m6;
-- Node name is 's0' = '|c60:15|74161:1|p74161:sub|QA'
-- Equation name is 's0', type is output
s0 = TFFE( VCC, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
-- Node name is 's1' = '|c60:15|74161:1|p74161:sub|QB'
-- Equation name is 's1', type is output
s1 = TFFE( s0, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
-- Node name is 's2' = '|c60:15|74161:1|p74161:sub|QC'
-- Equation name is 's2', type is output
s2 = TFFE( _EQ013, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ013 = s0 & s1 & !s2 & !s5
# s0 & s1 & !s2 & !s4
# s0 & s1 & !s2 & !s3
# s0 & s1 & s2;
-- Node name is 's3' = '|c60:15|74161:1|p74161:sub|QD'
-- Equation name is 's3', type is output
s3 = TFFE( _EQ014, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ014 = s0 & s1 & s3 & s4 & s5
# s0 & s1 & s2;
-- Node name is 's4' = '|c60:15|74161:2|p74161:sub|QA'
-- Equation name is 's4', type is output
s4 = TFFE( _EQ015, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ015 = s0 & s1 & s3 & s4 & s5
# s0 & s1 & s2 & s3;
-- Node name is 's5' = '|c60:15|74161:2|p74161:sub|QB'
-- Equation name is 's5', type is output
s5 = TFFE( _EQ016, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ016 = s0 & s1 & s2 & s3 & s4 & !s5
# s0 & s1 & s3 & s4 & s5;
-- Node name is 's6' = '|c60:15|74161:2|p74161:sub|QC'
-- Equation name is 's6', type is output
s6 = TFFE( _EQ017, GLOBAL( clk), GLOBAL( clr), VCC, VCC);
_EQ017 = s0 & s1 & s3 & s4 & s5 & s6;
-- Shareable expanders that are duplicated in multiple LABs:
-- (none)
Project Information e:\cpld1\clk60.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Standard
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'MAX7000S' family
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
PARALLEL_EXPANDERS = off
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SOFT_BUFFER_INSERTION = on
SUBFACTOR_EXTRACTION = on
TURBO_BIT = on
XOR_SYNTHESIS = on
IGNORE_SOFT_BUFFERS = off
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
One-Hot State Machine Encoding = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:00
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:00
Timing SNF Extractor 00:00:00
Assembler 00:00:01
-------------------------- --------
Total Time 00:00:01
Memory Allocated
-----------------
Peak memory allocated during compilation = 5,981K
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -