state.fit.qmsg

FPGA实验：用于检测输入的二进制系列

{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "4.279 ns register register " "Info: Estimated most critical path is register to register delay of 4.279 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[1\] 1 REG LAB_X26_Y3 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X26_Y3; Fanout = 9; REG Node = 'cnt\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt[1] } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.348 ns) + CELL(0.275 ns) 0.623 ns Mux0~127 2 COMB LAB_X26_Y3 1 " "Info: 2: + IC(0.348 ns) + CELL(0.275 ns) = 0.623 ns; Loc. = LAB_X26_Y3; Fanout = 1; COMB Node = 'Mux0~127'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.623 ns" { cnt[1] Mux0~127 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.271 ns) 1.184 ns Mux0~128 3 COMB LAB_X26_Y3 1 " "Info: 3: + IC(0.290 ns) + CELL(0.271 ns) = 1.184 ns; Loc. = LAB_X26_Y3; Fanout = 1; COMB Node = 'Mux0~128'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.561 ns" { Mux0~127 Mux0~128 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.415 ns) + CELL(0.150 ns) 1.749 ns Mux0~129 4 COMB LAB_X26_Y3 1 " "Info: 4: + IC(0.415 ns) + CELL(0.150 ns) = 1.749 ns; Loc. = LAB_X26_Y3; Fanout = 1; COMB Node = 'Mux0~129'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { Mux0~128 Mux0~129 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.290 ns) + CELL(0.271 ns) 2.310 ns Mux0~132 5 COMB LAB_X26_Y3 2 " "Info: 5: + IC(0.290 ns) + CELL(0.271 ns) = 2.310 ns; Loc. = LAB_X26_Y3; Fanout = 2; COMB Node = 'Mux0~132'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.561 ns" { Mux0~129 Mux0~132 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.145 ns) + CELL(0.420 ns) 2.875 ns Mux0~133 6 COMB LAB_X26_Y3 5 " "Info: 6: + IC(0.145 ns) + CELL(0.420 ns) = 2.875 ns; Loc. = LAB_X26_Y3; Fanout = 5; COMB Node = 'Mux0~133'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.565 ns" { Mux0~132 Mux0~133 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.127 ns) + CELL(0.437 ns) 3.439 ns Mux7~298 7 COMB LAB_X26_Y3 2 " "Info: 7: + IC(0.127 ns) + CELL(0.437 ns) = 3.439 ns; Loc. = LAB_X26_Y3; Fanout = 2; COMB Node = 'Mux7~298'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.564 ns" { Mux0~133 Mux7~298 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.336 ns) + CELL(0.420 ns) 4.195 ns Mux7~299 8 COMB LAB_X25_Y3 1 " "Info: 8: + IC(0.336 ns) + CELL(0.420 ns) = 4.195 ns; Loc. = LAB_X25_Y3; Fanout = 1; COMB Node = 'Mux7~299'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.756 ns" { Mux7~298 Mux7~299 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 4.279 ns next_state\[2\] 9 REG LAB_X25_Y3 1 " "Info: 9: + IC(0.000 ns) + CELL(0.084 ns) = 4.279 ns; Loc. = LAB_X25_Y3; Fanout = 1; REG Node = 'next_state\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Mux7~299 next_state[2] } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.328 ns ( 54.41 % ) " "Info: Total cell delay = 2.328 ns ( 54.41 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.951 ns ( 45.59 % ) " "Info: Total interconnect delay = 1.951 ns ( 45.59 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.279 ns" { cnt[1] Mux0~127 Mux0~128 Mux0~129 Mux0~132 Mux0~133 Mux7~298 Mux7~299 next_state[2] } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "1 " "Warning: Found 1 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "z 0 " "Info: Pin \"z\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1  Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 26 15:35:19 2008 " "Info: Processing ended: Sun Oct 26 15:35:19 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:10 " "Info: Elapsed time: 00:00:10" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/lessons/电路与系统/实验设计/实验/state/state.fit.smsg " "Info: Generated suppressed messages file E:/lessons/电路与系统/实验设计/实验/state/state.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}