state.tan.qmsg

FPGA实验：用于检测输入的二进制系列

{ "Info" "ITDB_TH_RESULT" "next_state\[7\] rst clk0 -1.111 ns register " "Info: th for register \"next_state\[7\]\" (data pin = \"rst\", clock pin = \"clk0\") is -1.111 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 2.370 ns + Longest register " "Info: + Longest clock path from clock \"clk0\" to destination register is 2.370 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk0 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk0~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk0~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk0 clk0~clkctrl } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.722 ns) + CELL(0.537 ns) 2.370 ns next_state\[7\] 3 REG LCFF_X27_Y3_N13 1 " "Info: 3: + IC(0.722 ns) + CELL(0.537 ns) = 2.370 ns; Loc. = LCFF_X27_Y3_N13; Fanout = 1; REG Node = 'next_state\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.259 ns" { clk0~clkctrl next_state[7] } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.39 % ) " "Info: Total cell delay = 1.526 ns ( 64.39 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.844 ns ( 35.61 % ) " "Info: Total interconnect delay = 0.844 ns ( 35.61 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.370 ns" { clk0 clk0~clkctrl next_state[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.370 ns" { clk0 clk0~combout clk0~clkctrl next_state[7] } { 0.000ns 0.000ns 0.122ns 0.722ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.747 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.747 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns rst 1 PIN PIN_21 2 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_21; Fanout = 2; PIN Node = 'rst'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.473 ns) + CELL(0.378 ns) 2.840 ns process1~0 2 COMB LCCOMB_X27_Y3_N20 10 " "Info: 2: + IC(1.473 ns) + CELL(0.378 ns) = 2.840 ns; Loc. = LCCOMB_X27_Y3_N20; Fanout = 10; COMB Node = 'process1~0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.851 ns" { rst process1~0 } "NODE_NAME" } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.247 ns) + CELL(0.660 ns) 3.747 ns next_state\[7\] 3 REG LCFF_X27_Y3_N13 1 " "Info: 3: + IC(0.247 ns) + CELL(0.660 ns) = 3.747 ns; Loc. = LCFF_X27_Y3_N13; Fanout = 1; REG Node = 'next_state\[7\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.907 ns" { process1~0 next_state[7] } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.027 ns ( 54.10 % ) " "Info: Total cell delay = 2.027 ns ( 54.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.720 ns ( 45.90 % ) " "Info: Total interconnect delay = 1.720 ns ( 45.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.747 ns" { rst process1~0 next_state[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.747 ns" { rst rst~combout process1~0 next_state[7] } { 0.000ns 0.000ns 1.473ns 0.247ns } { 0.000ns 0.989ns 0.378ns 0.660ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.370 ns" { clk0 clk0~clkctrl next_state[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.370 ns" { clk0 clk0~combout clk0~clkctrl next_state[7] } { 0.000ns 0.000ns 0.122ns 0.722ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.747 ns" { rst process1~0 next_state[7] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.747 ns" { rst rst~combout process1~0 next_state[7] } { 0.000ns 0.000ns 1.473ns 0.247ns } { 0.000ns 0.989ns 0.378ns 0.660ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 26 15:35:32 2008 " "Info: Processing ended: Sun Oct 26 15:35:32 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}