state.tan.qmsg

FPGA实验：用于检测输入的二进制系列

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk0 register cnt\[1\] register next_state\[2\] 268.67 MHz 3.722 ns Internal " "Info: Clock \"clk0\" has Internal fmax of 268.67 MHz between source register \"cnt\[1\]\" and destination register \"next_state\[2\]\" (period= 3.722 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.508 ns + Longest register register " "Info: + Longest register to register delay is 3.508 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns cnt\[1\] 1 REG LCFF_X26_Y3_N21 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y3_N21; Fanout = 9; REG Node = 'cnt\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { cnt[1] } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.271 ns) 0.813 ns Mux0~123 2 COMB LCCOMB_X27_Y3_N22 1 " "Info: 2: + IC(0.542 ns) + CELL(0.271 ns) = 0.813 ns; Loc. = LCCOMB_X27_Y3_N22; Fanout = 1; COMB Node = 'Mux0~123'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.813 ns" { cnt[1] Mux0~123 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.240 ns) + CELL(0.150 ns) 1.203 ns Mux0~124 3 COMB LCCOMB_X27_Y3_N30 1 " "Info: 3: + IC(0.240 ns) + CELL(0.150 ns) = 1.203 ns; Loc. = LCCOMB_X27_Y3_N30; Fanout = 1; COMB Node = 'Mux0~124'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.390 ns" { Mux0~123 Mux0~124 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.403 ns) + CELL(0.420 ns) 2.026 ns Mux0~132 4 COMB LCCOMB_X26_Y3_N6 2 " "Info: 4: + IC(0.403 ns) + CELL(0.420 ns) = 2.026 ns; Loc. = LCCOMB_X26_Y3_N6; Fanout = 2; COMB Node = 'Mux0~132'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.823 ns" { Mux0~124 Mux0~132 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.150 ns) 2.431 ns Mux0~133 5 COMB LCCOMB_X26_Y3_N28 5 " "Info: 5: + IC(0.255 ns) + CELL(0.150 ns) = 2.431 ns; Loc. = LCCOMB_X26_Y3_N28; Fanout = 5; COMB Node = 'Mux0~133'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.405 ns" { Mux0~132 Mux0~133 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.265 ns) + CELL(0.150 ns) 2.846 ns Mux7~298 6 COMB LCCOMB_X26_Y3_N30 2 " "Info: 6: + IC(0.265 ns) + CELL(0.150 ns) = 2.846 ns; Loc. = LCCOMB_X26_Y3_N30; Fanout = 2; COMB Node = 'Mux7~298'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.415 ns" { Mux0~133 Mux7~298 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.150 ns) 3.424 ns Mux7~299 7 COMB LCCOMB_X25_Y3_N20 1 " "Info: 7: + IC(0.428 ns) + CELL(0.150 ns) = 3.424 ns; Loc. = LCCOMB_X25_Y3_N20; Fanout = 1; COMB Node = 'Mux7~299'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.578 ns" { Mux7~298 Mux7~299 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 3.508 ns next_state\[2\] 8 REG LCFF_X25_Y3_N21 1 " "Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 3.508 ns; Loc. = LCFF_X25_Y3_N21; Fanout = 1; REG Node = 'next_state\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Mux7~299 next_state[2] } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.375 ns ( 39.20 % ) " "Info: Total cell delay = 1.375 ns ( 39.20 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.133 ns ( 60.80 % ) " "Info: Total interconnect delay = 2.133 ns ( 60.80 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.508 ns" { cnt[1] Mux0~123 Mux0~124 Mux0~132 Mux0~133 Mux7~298 Mux7~299 next_state[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.508 ns" { cnt[1] Mux0~123 Mux0~124 Mux0~132 Mux0~133 Mux7~298 Mux7~299 next_state[2] } { 0.000ns 0.542ns 0.240ns 0.403ns 0.255ns 0.265ns 0.428ns 0.000ns } { 0.000ns 0.271ns 0.150ns 0.420ns 0.150ns 0.150ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 2.368 ns + Shortest register " "Info: + Shortest clock path from clock \"clk0\" to destination register is 2.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk0 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk0~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk0~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk0 clk0~clkctrl } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.720 ns) + CELL(0.537 ns) 2.368 ns next_state\[2\] 3 REG LCFF_X25_Y3_N21 1 " "Info: 3: + IC(0.720 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X25_Y3_N21; Fanout = 1; REG Node = 'next_state\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.257 ns" { clk0~clkctrl next_state[2] } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.44 % ) " "Info: Total cell delay = 1.526 ns ( 64.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.842 ns ( 35.56 % ) " "Info: Total interconnect delay = 0.842 ns ( 35.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.368 ns" { clk0 clk0~clkctrl next_state[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.368 ns" { clk0 clk0~combout clk0~clkctrl next_state[2] } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 2.368 ns - Longest register " "Info: - Longest clock path from clock \"clk0\" to source register is 2.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk0 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk0~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk0~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk0 clk0~clkctrl } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.720 ns) + CELL(0.537 ns) 2.368 ns cnt\[1\] 3 REG LCFF_X26_Y3_N21 9 " "Info: 3: + IC(0.720 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X26_Y3_N21; Fanout = 9; REG Node = 'cnt\[1\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.257 ns" { clk0~clkctrl cnt[1] } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.44 % ) " "Info: Total cell delay = 1.526 ns ( 64.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.842 ns ( 35.56 % ) " "Info: Total interconnect delay = 0.842 ns ( 35.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.368 ns" { clk0 clk0~clkctrl cnt[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.368 ns" { clk0 clk0~combout clk0~clkctrl cnt[1] } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.368 ns" { clk0 clk0~clkctrl next_state[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.368 ns" { clk0 clk0~combout clk0~clkctrl next_state[2] } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.368 ns" { clk0 clk0~clkctrl cnt[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.368 ns" { clk0 clk0~combout clk0~clkctrl cnt[1] } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.508 ns" { cnt[1] Mux0~123 Mux0~124 Mux0~132 Mux0~133 Mux7~298 Mux7~299 next_state[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.508 ns" { cnt[1] Mux0~123 Mux0~124 Mux0~132 Mux0~133 Mux7~298 Mux7~299 next_state[2] } { 0.000ns 0.542ns 0.240ns 0.403ns 0.255ns 0.265ns 0.428ns 0.000ns } { 0.000ns 0.271ns 0.150ns 0.420ns 0.150ns 0.150ns 0.150ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.368 ns" { clk0 clk0~clkctrl next_state[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.368 ns" { clk0 clk0~combout clk0~clkctrl next_state[2] } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.368 ns" { clk0 clk0~clkctrl cnt[1] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.368 ns" { clk0 clk0~combout clk0~clkctrl cnt[1] } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "clk1 " "Info: No valid register-to-register data paths exist for clock \"clk1\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "next_state\[2\] w\[8\] clk0 6.795 ns register " "Info: tsu for register \"next_state\[2\]\" (data pin = \"w\[8\]\", clock pin = \"clk0\") is 6.795 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.199 ns + Longest pin register " "Info: + Longest pin to register delay is 9.199 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.850 ns) 0.850 ns w\[8\] 1 PIN PIN_113 1 " "Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_113; Fanout = 1; PIN Node = 'w\[8\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { w[8] } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 4 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.234 ns) + CELL(0.420 ns) 6.504 ns Mux0~123 2 COMB LCCOMB_X27_Y3_N22 1 " "Info: 2: + IC(5.234 ns) + CELL(0.420 ns) = 6.504 ns; Loc. = LCCOMB_X27_Y3_N22; Fanout = 1; COMB Node = 'Mux0~123'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.654 ns" { w[8] Mux0~123 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.240 ns) + CELL(0.150 ns) 6.894 ns Mux0~124 3 COMB LCCOMB_X27_Y3_N30 1 " "Info: 3: + IC(0.240 ns) + CELL(0.150 ns) = 6.894 ns; Loc. = LCCOMB_X27_Y3_N30; Fanout = 1; COMB Node = 'Mux0~124'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.390 ns" { Mux0~123 Mux0~124 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.403 ns) + CELL(0.420 ns) 7.717 ns Mux0~132 4 COMB LCCOMB_X26_Y3_N6 2 " "Info: 4: + IC(0.403 ns) + CELL(0.420 ns) = 7.717 ns; Loc. = LCCOMB_X26_Y3_N6; Fanout = 2; COMB Node = 'Mux0~132'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.823 ns" { Mux0~124 Mux0~132 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.255 ns) + CELL(0.150 ns) 8.122 ns Mux0~133 5 COMB LCCOMB_X26_Y3_N28 5 " "Info: 5: + IC(0.255 ns) + CELL(0.150 ns) = 8.122 ns; Loc. = LCCOMB_X26_Y3_N28; Fanout = 5; COMB Node = 'Mux0~133'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.405 ns" { Mux0~132 Mux0~133 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 37 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.265 ns) + CELL(0.150 ns) 8.537 ns Mux7~298 6 COMB LCCOMB_X26_Y3_N30 2 " "Info: 6: + IC(0.265 ns) + CELL(0.150 ns) = 8.537 ns; Loc. = LCCOMB_X26_Y3_N30; Fanout = 2; COMB Node = 'Mux7~298'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.415 ns" { Mux0~133 Mux7~298 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.428 ns) + CELL(0.150 ns) 9.115 ns Mux7~299 7 COMB LCCOMB_X25_Y3_N20 1 " "Info: 7: + IC(0.428 ns) + CELL(0.150 ns) = 9.115 ns; Loc. = LCCOMB_X25_Y3_N20; Fanout = 1; COMB Node = 'Mux7~299'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.578 ns" { Mux7~298 Mux7~299 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 38 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 9.199 ns next_state\[2\] 8 REG LCFF_X25_Y3_N21 1 " "Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 9.199 ns; Loc. = LCFF_X25_Y3_N21; Fanout = 1; REG Node = 'next_state\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { Mux7~299 next_state[2] } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.374 ns ( 25.81 % ) " "Info: Total cell delay = 2.374 ns ( 25.81 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.825 ns ( 74.19 % ) " "Info: Total interconnect delay = 6.825 ns ( 74.19 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.199 ns" { w[8] Mux0~123 Mux0~124 Mux0~132 Mux0~133 Mux7~298 Mux7~299 next_state[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.199 ns" { w[8] w[8]~combout Mux0~123 Mux0~124 Mux0~132 Mux0~133 Mux7~298 Mux7~299 next_state[2] } { 0.000ns 0.000ns 5.234ns 0.240ns 0.403ns 0.255ns 0.265ns 0.428ns 0.000ns } { 0.000ns 0.850ns 0.420ns 0.150ns 0.420ns 0.150ns 0.150ns 0.150ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 destination 2.368 ns - Shortest register " "Info: - Shortest clock path from clock \"clk0\" to destination register is 2.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk0 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk0~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk0~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk0 clk0~clkctrl } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.720 ns) + CELL(0.537 ns) 2.368 ns next_state\[2\] 3 REG LCFF_X25_Y3_N21 1 " "Info: 3: + IC(0.720 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X25_Y3_N21; Fanout = 1; REG Node = 'next_state\[2\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.257 ns" { clk0~clkctrl next_state[2] } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.44 % ) " "Info: Total cell delay = 1.526 ns ( 64.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.842 ns ( 35.56 % ) " "Info: Total interconnect delay = 0.842 ns ( 35.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.368 ns" { clk0 clk0~clkctrl next_state[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.368 ns" { clk0 clk0~combout clk0~clkctrl next_state[2] } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "9.199 ns" { w[8] Mux0~123 Mux0~124 Mux0~132 Mux0~133 Mux7~298 Mux7~299 next_state[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "9.199 ns" { w[8] w[8]~combout Mux0~123 Mux0~124 Mux0~132 Mux0~133 Mux7~298 Mux7~299 next_state[2] } { 0.000ns 0.000ns 5.234ns 0.240ns 0.403ns 0.255ns 0.265ns 0.428ns 0.000ns } { 0.000ns 0.850ns 0.420ns 0.150ns 0.420ns 0.150ns 0.150ns 0.150ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.368 ns" { clk0 clk0~clkctrl next_state[2] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.368 ns" { clk0 clk0~combout clk0~clkctrl next_state[2] } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk0 z z~reg0 6.444 ns register " "Info: tco from clock \"clk0\" to destination pin \"z\" through register \"z~reg0\" is 6.444 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk0 source 2.368 ns + Longest register " "Info: + Longest clock path from clock \"clk0\" to source register is 2.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.989 ns) 0.989 ns clk0 1 CLK PIN_17 1 " "Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk0 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.111 ns clk0~clkctrl 2 COMB CLKCTRL_G2 14 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk0~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { clk0 clk0~clkctrl } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 5 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.720 ns) + CELL(0.537 ns) 2.368 ns z~reg0 3 REG LCFF_X25_Y3_N15 3 " "Info: 3: + IC(0.720 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X25_Y3_N15; Fanout = 3; REG Node = 'z~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.257 ns" { clk0~clkctrl z~reg0 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.526 ns ( 64.44 % ) " "Info: Total cell delay = 1.526 ns ( 64.44 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.842 ns ( 35.56 % ) " "Info: Total interconnect delay = 0.842 ns ( 35.56 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.368 ns" { clk0 clk0~clkctrl z~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.368 ns" { clk0 clk0~combout clk0~clkctrl z~reg0 } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.826 ns + Longest register pin " "Info: + Longest register to pin delay is 3.826 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns z~reg0 1 REG LCFF_X25_Y3_N15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y3_N15; Fanout = 3; REG Node = 'z~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { z~reg0 } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.028 ns) + CELL(2.798 ns) 3.826 ns z 2 PIN PIN_65 0 " "Info: 2: + IC(1.028 ns) + CELL(2.798 ns) = 3.826 ns; Loc. = PIN_65; Fanout = 0; PIN Node = 'z'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.826 ns" { z~reg0 z } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/state/state.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 73.13 % ) " "Info: Total cell delay = 2.798 ns ( 73.13 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.028 ns ( 26.87 % ) " "Info: Total interconnect delay = 1.028 ns ( 26.87 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.826 ns" { z~reg0 z } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.826 ns" { z~reg0 z } { 0.000ns 1.028ns } { 0.000ns 2.798ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.368 ns" { clk0 clk0~clkctrl z~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.368 ns" { clk0 clk0~combout clk0~clkctrl z~reg0 } { 0.000ns 0.000ns 0.122ns 0.720ns } { 0.000ns 0.989ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "3.826 ns" { z~reg0 z } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "3.826 ns" { z~reg0 z } { 0.000ns 1.028ns } { 0.000ns 2.798ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}