state.tan.rpt

FPGA实验：用于检测输入的二进制系列

; N/A           ; None        ; -5.859 ns ; w[5]  ; next_state[3] ; clk0     ;
; N/A           ; None        ; -5.862 ns ; w[5]  ; next_state[5] ; clk0     ;
; N/A           ; None        ; -5.862 ns ; w[13] ; next_state[7] ; clk0     ;
; N/A           ; None        ; -5.875 ns ; w[6]  ; next_state[2] ; clk0     ;
; N/A           ; None        ; -5.878 ns ; w[10] ; next_state[4] ; clk0     ;
; N/A           ; None        ; -5.879 ns ; w[10] ; next_state[0] ; clk0     ;
; N/A           ; None        ; -5.896 ns ; w[5]  ; next_state[1] ; clk0     ;
; N/A           ; None        ; -5.952 ns ; w[8]  ; next_state[7] ; clk0     ;
; N/A           ; None        ; -5.972 ns ; w[12] ; next_state[6] ; clk0     ;
; N/A           ; None        ; -5.972 ns ; w[12] ; next_state[3] ; clk0     ;
; N/A           ; None        ; -5.973 ns ; w[9]  ; next_state[2] ; clk0     ;
; N/A           ; None        ; -5.975 ns ; w[12] ; next_state[5] ; clk0     ;
; N/A           ; None        ; -6.009 ns ; w[12] ; next_state[1] ; clk0     ;
; N/A           ; None        ; -6.019 ns ; w[3]  ; next_state[6] ; clk0     ;
; N/A           ; None        ; -6.019 ns ; w[3]  ; next_state[3] ; clk0     ;
; N/A           ; None        ; -6.022 ns ; w[3]  ; next_state[5] ; clk0     ;
; N/A           ; None        ; -6.025 ns ; w[5]  ; next_state[2] ; clk0     ;
; N/A           ; None        ; -6.056 ns ; w[3]  ; next_state[1] ; clk0     ;
; N/A           ; None        ; -6.086 ns ; w[10] ; next_state[6] ; clk0     ;
; N/A           ; None        ; -6.086 ns ; w[10] ; next_state[3] ; clk0     ;
; N/A           ; None        ; -6.089 ns ; w[10] ; next_state[5] ; clk0     ;
; N/A           ; None        ; -6.096 ns ; w[0]  ; next_state[4] ; clk0     ;
; N/A           ; None        ; -6.097 ns ; w[0]  ; next_state[0] ; clk0     ;
; N/A           ; None        ; -6.101 ns ; w[13] ; next_state[4] ; clk0     ;
; N/A           ; None        ; -6.102 ns ; w[13] ; next_state[0] ; clk0     ;
; N/A           ; None        ; -6.123 ns ; w[10] ; next_state[1] ; clk0     ;
; N/A           ; None        ; -6.138 ns ; w[12] ; next_state[2] ; clk0     ;
; N/A           ; None        ; -6.185 ns ; w[3]  ; next_state[2] ; clk0     ;
; N/A           ; None        ; -6.191 ns ; w[8]  ; next_state[4] ; clk0     ;
; N/A           ; None        ; -6.192 ns ; w[8]  ; next_state[0] ; clk0     ;
; N/A           ; None        ; -6.252 ns ; w[10] ; next_state[2] ; clk0     ;
; N/A           ; None        ; -6.304 ns ; w[0]  ; next_state[6] ; clk0     ;
; N/A           ; None        ; -6.304 ns ; w[0]  ; next_state[3] ; clk0     ;
; N/A           ; None        ; -6.307 ns ; w[0]  ; next_state[5] ; clk0     ;
; N/A           ; None        ; -6.309 ns ; w[13] ; next_state[6] ; clk0     ;
; N/A           ; None        ; -6.309 ns ; w[13] ; next_state[3] ; clk0     ;
; N/A           ; None        ; -6.312 ns ; w[13] ; next_state[5] ; clk0     ;
; N/A           ; None        ; -6.341 ns ; w[0]  ; next_state[1] ; clk0     ;
; N/A           ; None        ; -6.346 ns ; w[13] ; next_state[1] ; clk0     ;
; N/A           ; None        ; -6.399 ns ; w[8]  ; next_state[6] ; clk0     ;
; N/A           ; None        ; -6.399 ns ; w[8]  ; next_state[3] ; clk0     ;
; N/A           ; None        ; -6.402 ns ; w[8]  ; next_state[5] ; clk0     ;
; N/A           ; None        ; -6.436 ns ; w[8]  ; next_state[1] ; clk0     ;
; N/A           ; None        ; -6.470 ns ; w[0]  ; next_state[2] ; clk0     ;
; N/A           ; None        ; -6.475 ns ; w[13] ; next_state[2] ; clk0     ;
; N/A           ; None        ; -6.565 ns ; w[8]  ; next_state[2] ; clk0     ;
+---------------+-------------+-----------+-------+---------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Sun Oct 26 15:35:31 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off state -c state --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk0" is an undefined clock
    Info: Assuming node "clk1" is an undefined clock
Info: Clock "clk0" has Internal fmax of 268.67 MHz between source register "cnt[1]" and destination register "next_state[2]" (period= 3.722 ns)
    Info: + Longest register to register delay is 3.508 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X26_Y3_N21; Fanout = 9; REG Node = 'cnt[1]'
        Info: 2: + IC(0.542 ns) + CELL(0.271 ns) = 0.813 ns; Loc. = LCCOMB_X27_Y3_N22; Fanout = 1; COMB Node = 'Mux0~123'
        Info: 3: + IC(0.240 ns) + CELL(0.150 ns) = 1.203 ns; Loc. = LCCOMB_X27_Y3_N30; Fanout = 1; COMB Node = 'Mux0~124'
        Info: 4: + IC(0.403 ns) + CELL(0.420 ns) = 2.026 ns; Loc. = LCCOMB_X26_Y3_N6; Fanout = 2; COMB Node = 'Mux0~132'
        Info: 5: + IC(0.255 ns) + CELL(0.150 ns) = 2.431 ns; Loc. = LCCOMB_X26_Y3_N28; Fanout = 5; COMB Node = 'Mux0~133'
        Info: 6: + IC(0.265 ns) + CELL(0.150 ns) = 2.846 ns; Loc. = LCCOMB_X26_Y3_N30; Fanout = 2; COMB Node = 'Mux7~298'
        Info: 7: + IC(0.428 ns) + CELL(0.150 ns) = 3.424 ns; Loc. = LCCOMB_X25_Y3_N20; Fanout = 1; COMB Node = 'Mux7~299'
        Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 3.508 ns; Loc. = LCFF_X25_Y3_N21; Fanout = 1; REG Node = 'next_state[2]'
        Info: Total cell delay = 1.375 ns ( 39.20 % )
        Info: Total interconnect delay = 2.133 ns ( 60.80 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk0" to destination register is 2.368 ns
            Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk0'
            Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk0~clkctrl'
            Info: 3: + IC(0.720 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X25_Y3_N21; Fanout = 1; REG Node = 'next_state[2]'
            Info: Total cell delay = 1.526 ns ( 64.44 % )
            Info: Total interconnect delay = 0.842 ns ( 35.56 % )
        Info: - Longest clock path from clock "clk0" to source register is 2.368 ns
            Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk0'
            Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk0~clkctrl'
            Info: 3: + IC(0.720 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X26_Y3_N21; Fanout = 9; REG Node = 'cnt[1]'
            Info: Total cell delay = 1.526 ns ( 64.44 % )
            Info: Total interconnect delay = 0.842 ns ( 35.56 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: No valid register-to-register data paths exist for clock "clk1"
Info: tsu for register "next_state[2]" (data pin = "w[8]", clock pin = "clk0") is 6.795 ns
    Info: + Longest pin to register delay is 9.199 ns
        Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_113; Fanout = 1; PIN Node = 'w[8]'
        Info: 2: + IC(5.234 ns) + CELL(0.420 ns) = 6.504 ns; Loc. = LCCOMB_X27_Y3_N22; Fanout = 1; COMB Node = 'Mux0~123'
        Info: 3: + IC(0.240 ns) + CELL(0.150 ns) = 6.894 ns; Loc. = LCCOMB_X27_Y3_N30; Fanout = 1; COMB Node = 'Mux0~124'
        Info: 4: + IC(0.403 ns) + CELL(0.420 ns) = 7.717 ns; Loc. = LCCOMB_X26_Y3_N6; Fanout = 2; COMB Node = 'Mux0~132'
        Info: 5: + IC(0.255 ns) + CELL(0.150 ns) = 8.122 ns; Loc. = LCCOMB_X26_Y3_N28; Fanout = 5; COMB Node = 'Mux0~133'
        Info: 6: + IC(0.265 ns) + CELL(0.150 ns) = 8.537 ns; Loc. = LCCOMB_X26_Y3_N30; Fanout = 2; COMB Node = 'Mux7~298'
        Info: 7: + IC(0.428 ns) + CELL(0.150 ns) = 9.115 ns; Loc. = LCCOMB_X25_Y3_N20; Fanout = 1; COMB Node = 'Mux7~299'
        Info: 8: + IC(0.000 ns) + CELL(0.084 ns) = 9.199 ns; Loc. = LCFF_X25_Y3_N21; Fanout = 1; REG Node = 'next_state[2]'
        Info: Total cell delay = 2.374 ns ( 25.81 % )
        Info: Total interconnect delay = 6.825 ns ( 74.19 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "clk0" to destination register is 2.368 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk0'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk0~clkctrl'
        Info: 3: + IC(0.720 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X25_Y3_N21; Fanout = 1; REG Node = 'next_state[2]'
        Info: Total cell delay = 1.526 ns ( 64.44 % )
        Info: Total interconnect delay = 0.842 ns ( 35.56 % )
Info: tco from clock "clk0" to destination pin "z" through register "z~reg0" is 6.444 ns
    Info: + Longest clock path from clock "clk0" to source register is 2.368 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk0'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk0~clkctrl'
        Info: 3: + IC(0.720 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X25_Y3_N15; Fanout = 3; REG Node = 'z~reg0'
        Info: Total cell delay = 1.526 ns ( 64.44 % )
        Info: Total interconnect delay = 0.842 ns ( 35.56 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 3.826 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X25_Y3_N15; Fanout = 3; REG Node = 'z~reg0'
        Info: 2: + IC(1.028 ns) + CELL(2.798 ns) = 3.826 ns; Loc. = PIN_65; Fanout = 0; PIN Node = 'z'
        Info: Total cell delay = 2.798 ns ( 73.13 % )
        Info: Total interconnect delay = 1.028 ns ( 26.87 % )
Info: th for register "next_state[7]" (data pin = "rst", clock pin = "clk0") is -1.111 ns
    Info: + Longest clock path from clock "clk0" to destination register is 2.370 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk0'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 14; COMB Node = 'clk0~clkctrl'
        Info: 3: + IC(0.722 ns) + CELL(0.537 ns) = 2.370 ns; Loc. = LCFF_X27_Y3_N13; Fanout = 1; REG Node = 'next_state[7]'
        Info: Total cell delay = 1.526 ns ( 64.39 % )
        Info: Total interconnect delay = 0.844 ns ( 35.61 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 3.747 ns
        Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_21; Fanout = 2; PIN Node = 'rst'
        Info: 2: + IC(1.473 ns) + CELL(0.378 ns) = 2.840 ns; Loc. = LCCOMB_X27_Y3_N20; Fanout = 10; COMB Node = 'process1~0'
        Info: 3: + IC(0.247 ns) + CELL(0.660 ns) = 3.747 ns; Loc. = LCFF_X27_Y3_N13; Fanout = 1; REG Node = 'next_state[7]'
        Info: Total cell delay = 2.027 ns ( 54.10 % )
        Info: Total interconnect delay = 1.720 ns ( 45.90 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sun Oct 26 15:35:32 2008
    Info: Elapsed time: 00:00:02