📄 state.tan.rpt
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Timing Analyzer report for state
Sun Oct 26 15:35:32 2008
Version 6.0 Build 178 04/27/2006 SJ Web Edition
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; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'clk0'
6. tsu
7. tco
8. th
9. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2006 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+--------+---------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+--------+---------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 6.795 ns ; w[8] ; next_state[2] ; -- ; clk0 ; 0 ;
; Worst-case tco ; N/A ; None ; 6.444 ns ; z~reg0 ; z ; clk0 ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -1.111 ns ; rst ; next_state[7] ; -- ; clk0 ; 0 ;
; Clock Setup: 'clk0' ; N/A ; None ; 268.67 MHz ( period = 3.722 ns ) ; cnt[1] ; next_state[2] ; clk0 ; clk0 ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+--------+---------------+------------+----------+--------------+
+------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+-------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C5T144C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Default hold multicycle ; Same As Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
+-------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk0 ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
; clk1 ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk0' ;
+-------+------------------------------------------------+--------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-------+------------------------------------------------+--------+---------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 268.67 MHz ( period = 3.722 ns ) ; cnt[1] ; next_state[2] ; clk0 ; clk0 ; None ; None ; 3.508 ns ;
; N/A ; 278.32 MHz ( period = 3.593 ns ) ; cnt[1] ; next_state[1] ; clk0 ; clk0 ; None ; None ; 3.379 ns ;
; N/A ; 279.96 MHz ( period = 3.572 ns ) ; cnt[2] ; next_state[2] ; clk0 ; clk0 ; None ; None ; 3.358 ns ;
; N/A ; 280.98 MHz ( period = 3.559 ns ) ; cnt[1] ; next_state[5] ; clk0 ; clk0 ; None ; None ; 3.345 ns ;
; N/A ; 281.21 MHz ( period = 3.556 ns ) ; cnt[1] ; next_state[6] ; clk0 ; clk0 ; None ; None ; 3.342 ns ;
; N/A ; 281.21 MHz ( period = 3.556 ns ) ; cnt[1] ; next_state[3] ; clk0 ; clk0 ; None ; None ; 3.342 ns ;
; N/A ; 290.44 MHz ( period = 3.443 ns ) ; cnt[2] ; next_state[1] ; clk0 ; clk0 ; None ; None ; 3.229 ns ;
; N/A ; 293.34 MHz ( period = 3.409 ns ) ; cnt[2] ; next_state[5] ; clk0 ; clk0 ; None ; None ; 3.195 ns ;
; N/A ; 293.60 MHz ( period = 3.406 ns ) ; cnt[2] ; next_state[6] ; clk0 ; clk0 ; None ; None ; 3.192 ns ;
; N/A ; 293.60 MHz ( period = 3.406 ns ) ; cnt[2] ; next_state[3] ; clk0 ; clk0 ; None ; None ; 3.192 ns ;
; N/A ; 298.60 MHz ( period = 3.349 ns ) ; cnt[1] ; next_state[0] ; clk0 ; clk0 ; None ; None ; 3.135 ns ;
; N/A ; 298.69 MHz ( period = 3.348 ns ) ; cnt[1] ; next_state[4] ; clk0 ; clk0 ; None ; None ; 3.134 ns ;
; N/A ; 312.60 MHz ( period = 3.199 ns ) ; cnt[2] ; next_state[0] ; clk0 ; clk0 ; None ; None ; 2.985 ns ;
; N/A ; 312.70 MHz ( period = 3.198 ns ) ; cnt[2] ; next_state[4] ; clk0 ; clk0 ; None ; None ; 2.984 ns ;
; N/A ; 321.65 MHz ( period = 3.109 ns ) ; cnt[1] ; next_state[7] ; clk0 ; clk0 ; None ; None ; 2.897 ns ;
; N/A ; 327.87 MHz ( period = 3.050 ns ) ; cnt[2] ; z~reg0 ; clk0 ; clk0 ; None ; None ; 2.836 ns ;
; N/A ; 330.69 MHz ( period = 3.024 ns ) ; cnt[0] ; next_state[2] ; clk0 ; clk0 ; None ; None ; 2.808 ns ;
; N/A ; 337.95 MHz ( period = 2.959 ns ) ; cnt[2] ; next_state[7] ; clk0 ; clk0 ; None ; None ; 2.747 ns ;
; N/A ; 339.21 MHz ( period = 2.948 ns ) ; cnt[3] ; z~reg0 ; clk0 ; clk0 ; None ; None ; 2.734 ns ;
; N/A ; 339.21 MHz ( period = 2.948 ns ) ; cnt[3] ; next_state[4] ; clk0 ; clk0 ; None ; None ; 2.734 ns ;
; N/A ; 339.21 MHz ( period = 2.948 ns ) ; cnt[3] ; next_state[0] ; clk0 ; clk0 ; None ; None ; 2.734 ns ;
; N/A ; 339.21 MHz ( period = 2.948 ns ) ; cnt[3] ; next_state[1] ; clk0 ; clk0 ; None ; None ; 2.734 ns ;
; N/A ; 339.21 MHz ( period = 2.948 ns ) ; cnt[3] ; next_state[2] ; clk0 ; clk0 ; None ; None ; 2.734 ns ;
; N/A ; 344.23 MHz ( period = 2.905 ns ) ; cnt[1] ; z~reg0 ; clk0 ; clk0 ; None ; None ; 2.691 ns ;
; N/A ; 345.42 MHz ( period = 2.895 ns ) ; cnt[0] ; next_state[1] ; clk0 ; clk0 ; None ; None ; 2.679 ns ;
; N/A ; 349.53 MHz ( period = 2.861 ns ) ; cnt[0] ; next_state[5] ; clk0 ; clk0 ; None ; None ; 2.645 ns ;
; N/A ; 349.90 MHz ( period = 2.858 ns ) ; cnt[0] ; next_state[6] ; clk0 ; clk0 ; None ; None ; 2.642 ns ;
; N/A ; 349.90 MHz ( period = 2.858 ns ) ; cnt[0] ; next_state[3] ; clk0 ; clk0 ; None ; None ; 2.642 ns ;
; N/A ; 354.36 MHz ( period = 2.822 ns ) ; cnt[0] ; z~reg0 ; clk0 ; clk0 ; None ; None ; 2.606 ns ;
; N/A ; 354.36 MHz ( period = 2.822 ns ) ; cnt[0] ; next_state[4] ; clk0 ; clk0 ; None ; None ; 2.606 ns ;
; N/A ; 354.36 MHz ( period = 2.822 ns ) ; cnt[0] ; next_state[0] ; clk0 ; clk0 ; None ; None ; 2.606 ns ;
; N/A ; 366.84 MHz ( period = 2.726 ns ) ; cnt[3] ; next_state[6] ; clk0 ; clk0 ; None ; None ; 2.512 ns ;
; N/A ; 366.84 MHz ( period = 2.726 ns ) ; cnt[3] ; next_state[3] ; clk0 ; clk0 ; None ; None ; 2.512 ns ;
; N/A ; 366.84 MHz ( period = 2.726 ns ) ; cnt[3] ; next_state[5] ; clk0 ; clk0 ; None ; None ; 2.512 ns ;
; N/A ; 393.55 MHz ( period = 2.541 ns ) ; cnt[3] ; next_state[7] ; clk0 ; clk0 ; None ; None ; 2.329 ns ;
; N/A ; 414.08 MHz ( period = 2.415 ns ) ; cnt[0] ; next_state[7] ; clk0 ; clk0 ; None ; None ; 2.201 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[4] ; z~reg0 ; clk0 ; clk0 ; None ; None ; 1.972 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[4] ; next_state[4] ; clk0 ; clk0 ; None ; None ; 1.972 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[4] ; next_state[0] ; clk0 ; clk0 ; None ; None ; 1.972 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[4] ; next_state[1] ; clk0 ; clk0 ; None ; None ; 1.972 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[4] ; next_state[2] ; clk0 ; clk0 ; None ; None ; 1.972 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1] ; cnt[4] ; clk0 ; clk0 ; None ; None ; 1.773 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[4] ; next_state[6] ; clk0 ; clk0 ; None ; None ; 1.750 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[4] ; next_state[3] ; clk0 ; clk0 ; None ; None ; 1.750 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[4] ; next_state[5] ; clk0 ; clk0 ; None ; None ; 1.750 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1] ; cnt[3] ; clk0 ; clk0 ; None ; None ; 1.702 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; z~reg0 ; z~reg0 ; clk0 ; clk0 ; None ; None ; 1.679 ns ;
; N/A ; Restricted to 420.17 MHz ( period = 2.380 ns ) ; cnt[1] ; cnt[2] ; clk0 ; clk0 ; None ; None ; 1.631 ns ;
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