series.tan.qmsg

FPGA实验：用于检测输入的二进制系列

{ "Info" "ITDB_TH_RESULT" "keycod\[8\]~reg0 keyin8 rst 1.025 ns register " "Info: th for register \"keycod\[8\]~reg0\" (data pin = \"keyin8\", clock pin = \"rst\") is 1.025 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rst destination 2.340 ns + Longest register " "Info: + Longest clock path from clock \"rst\" to destination register is 2.340 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns rst 1 CLK PIN_18 3 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_18; Fanout = 3; CLK Node = 'rst'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series/series.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns rst~clkctrl 2 COMB CLKCTRL_G1 49 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G1; Fanout = 49; COMB Node = 'rst~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.122 ns" { rst rst~clkctrl } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series/series.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.702 ns) + CELL(0.537 ns) 2.340 ns keycod\[8\]~reg0 3 REG LCFF_X27_Y7_N1 1 " "Info: 3: + IC(0.702 ns) + CELL(0.537 ns) = 2.340 ns; Loc. = LCFF_X27_Y7_N1; Fanout = 1; REG Node = 'keycod\[8\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.239 ns" { rst~clkctrl keycod[8]~reg0 } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series/series.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.79 % ) " "Info: Total cell delay = 1.516 ns ( 64.79 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.824 ns ( 35.21 % ) " "Info: Total interconnect delay = 0.824 ns ( 35.21 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.340 ns" { rst rst~clkctrl keycod[8]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.340 ns" { rst rst~combout rst~clkctrl keycod[8]~reg0 } { 0.000ns 0.000ns 0.122ns 0.702ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series/series.vhd" 75 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.581 ns - Shortest pin register " "Info: - Shortest pin to register delay is 1.581 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns keyin8 1 PIN PIN_89 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_89; Fanout = 1; PIN Node = 'keyin8'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { keyin8 } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series/series.vhd" 17 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.349 ns) + CELL(0.149 ns) 1.497 ns keycod\[8\]~reg0feeder 2 COMB LCCOMB_X27_Y7_N0 1 " "Info: 2: + IC(0.349 ns) + CELL(0.149 ns) = 1.497 ns; Loc. = LCCOMB_X27_Y7_N0; Fanout = 1; COMB Node = 'keycod\[8\]~reg0feeder'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.498 ns" { keyin8 keycod[8]~reg0feeder } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series/series.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.581 ns keycod\[8\]~reg0 3 REG LCFF_X27_Y7_N1 1 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 1.581 ns; Loc. = LCFF_X27_Y7_N1; Fanout = 1; REG Node = 'keycod\[8\]~reg0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { keycod[8]~reg0feeder keycod[8]~reg0 } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series/series.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.232 ns ( 77.93 % ) " "Info: Total cell delay = 1.232 ns ( 77.93 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.349 ns ( 22.07 % ) " "Info: Total interconnect delay = 0.349 ns ( 22.07 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { keyin8 keycod[8]~reg0feeder keycod[8]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.581 ns" { keyin8 keyin8~combout keycod[8]~reg0feeder keycod[8]~reg0 } { 0.000ns 0.000ns 0.349ns 0.000ns } { 0.000ns 0.999ns 0.149ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.340 ns" { rst rst~clkctrl keycod[8]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.340 ns" { rst rst~combout rst~clkctrl keycod[8]~reg0 } { 0.000ns 0.000ns 0.122ns 0.702ns } { 0.000ns 0.979ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.581 ns" { keyin8 keycod[8]~reg0feeder keycod[8]~reg0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "1.581 ns" { keyin8 keyin8~combout keycod[8]~reg0feeder keycod[8]~reg0 } { 0.000ns 0.000ns 0.349ns 0.000ns } { 0.000ns 0.999ns 0.149ns 0.084ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Sun Oct 26 15:31:48 2008 " "Info: Processing ended: Sun Oct 26 15:31:48 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}