series.tan.summary

FPGA实验：用于检测输入的二进制系列

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 4.206 ns
From           : keyin0
To             : keycod[0]~reg0
From Clock     : --
To Clock       : rst
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 6.810 ns
From           : keycod[5]~reg0
To             : keycod[5]
From Clock     : rst
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 1.025 ns
From           : keyin8
To             : keycod[8]~reg0
From Clock     : --
To Clock       : rst
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 345.90 MHz ( period = 2.891 ns )
From           : cntfrq1[12]
To             : clkfrq1
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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