series.tan.rpt

FPGA实验：用于检测输入的二进制系列

; N/A   ; None         ; 6.070 ns   ; keycod[3]~reg0  ; keycod[3]  ; rst        ;
; N/A   ; None         ; 6.069 ns   ; keycod[16]~reg0 ; keycod[16] ; rst        ;
; N/A   ; None         ; 6.032 ns   ; keycod[4]~reg0  ; keycod[4]  ; rst        ;
; N/A   ; None         ; 5.953 ns   ; keycod[14]~reg0 ; keycod[14] ; rst        ;
; N/A   ; None         ; 5.909 ns   ; keycod[11]~reg0 ; keycod[11] ; rst        ;
; N/A   ; None         ; 5.875 ns   ; keycod[8]~reg0  ; keycod[8]  ; rst        ;
; N/A   ; None         ; 5.783 ns   ; keycod[12]~reg0 ; keycod[12] ; rst        ;
; N/A   ; None         ; 5.759 ns   ; keycod[15]~reg0 ; keycod[15] ; rst        ;
+-------+--------------+------------+-----------------+------------+------------+


+--------------------------------------------------------------------------------+
; th                                                                             ;
+---------------+-------------+-----------+---------+-----------------+----------+
; Minimum Slack ; Required th ; Actual th ; From    ; To              ; To Clock ;
+---------------+-------------+-----------+---------+-----------------+----------+
; N/A           ; None        ; 1.025 ns  ; keyin8  ; keycod[8]~reg0  ; rst      ;
; N/A           ; None        ; 0.794 ns  ; keyin7  ; keycod[7]~reg0  ; rst      ;
; N/A           ; None        ; 0.664 ns  ; keyin9  ; keycod[9]~reg0  ; rst      ;
; N/A           ; None        ; 0.663 ns  ; keyin10 ; keycod[10]~reg0 ; rst      ;
; N/A           ; None        ; -0.618 ns ; rst     ; clk1~reg0       ; clk      ;
; N/A           ; None        ; -0.896 ns ; rst     ; clk0~reg0       ; clk      ;
; N/A           ; None        ; -2.931 ns ; keyin15 ; keycod[15]~reg0 ; rst      ;
; N/A           ; None        ; -2.940 ns ; keyin11 ; keycod[11]~reg0 ; rst      ;
; N/A           ; None        ; -3.140 ns ; keyin16 ; keycod[16]~reg0 ; rst      ;
; N/A           ; None        ; -3.245 ns ; keyin2  ; keycod[2]~reg0  ; rst      ;
; N/A           ; None        ; -3.268 ns ; keyin1  ; keycod[1]~reg0  ; rst      ;
; N/A           ; None        ; -3.269 ns ; keyin14 ; keycod[14]~reg0 ; rst      ;
; N/A           ; None        ; -3.396 ns ; keyin6  ; keycod[6]~reg0  ; rst      ;
; N/A           ; None        ; -3.401 ns ; keyin13 ; keycod[13]~reg0 ; rst      ;
; N/A           ; None        ; -3.410 ns ; keyin3  ; keycod[3]~reg0  ; rst      ;
; N/A           ; None        ; -3.608 ns ; keyin4  ; keycod[4]~reg0  ; rst      ;
; N/A           ; None        ; -3.808 ns ; keyin12 ; keycod[12]~reg0 ; rst      ;
; N/A           ; None        ; -3.817 ns ; keyin5  ; keycod[5]~reg0  ; rst      ;
; N/A           ; None        ; -3.976 ns ; keyin0  ; keycod[0]~reg0  ; rst      ;
+---------------+-------------+-----------+---------+-----------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
    Info: Processing started: Sun Oct 26 15:31:47 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off series -c series --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
    Info: Assuming node "rst" is an undefined clock
Info: Clock "clk" has Internal fmax of 345.9 MHz between source register "cntfrq1[12]" and destination register "clkfrq1" (period= 2.891 ns)
    Info: + Longest register to register delay is 2.692 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y11_N27; Fanout = 3; REG Node = 'cntfrq1[12]'
        Info: 2: + IC(0.529 ns) + CELL(0.275 ns) = 0.804 ns; Loc. = LCCOMB_X14_Y11_N0; Fanout = 1; COMB Node = 'Equal1~144'
        Info: 3: + IC(0.754 ns) + CELL(0.410 ns) = 1.968 ns; Loc. = LCCOMB_X13_Y11_N24; Fanout = 4; COMB Node = 'Equal1~145'
        Info: 4: + IC(0.490 ns) + CELL(0.150 ns) = 2.608 ns; Loc. = LCCOMB_X13_Y11_N0; Fanout = 1; COMB Node = 'clkfrq1~47'
        Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 2.692 ns; Loc. = LCFF_X13_Y11_N1; Fanout = 2; REG Node = 'clkfrq1'
        Info: Total cell delay = 0.919 ns ( 34.14 % )
        Info: Total interconnect delay = 1.773 ns ( 65.86 % )
    Info: - Smallest clock skew is 0.015 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.374 ns
            Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.726 ns) + CELL(0.537 ns) = 2.374 ns; Loc. = LCFF_X13_Y11_N1; Fanout = 2; REG Node = 'clkfrq1'
            Info: Total cell delay = 1.526 ns ( 64.28 % )
            Info: Total interconnect delay = 0.848 ns ( 35.72 % )
        Info: - Longest clock path from clock "clk" to source register is 2.359 ns
            Info: 1: + IC(0.000 ns) + CELL(0.989 ns) = 0.989 ns; Loc. = PIN_17; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.111 ns; Loc. = CLKCTRL_G2; Fanout = 34; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.711 ns) + CELL(0.537 ns) = 2.359 ns; Loc. = LCFF_X14_Y11_N27; Fanout = 3; REG Node = 'cntfrq1[12]'
            Info: Total cell delay = 1.526 ns ( 64.69 % )
            Info: Total interconnect delay = 0.833 ns ( 35.31 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: No valid register-to-register data paths exist for clock "rst"
Info: tsu for register "keycod[0]~reg0" (data pin = "keyin0", clock pin = "rst") is 4.206 ns
    Info: + Longest pin to register delay is 6.601 ns
        Info: 1: + IC(0.000 ns) + CELL(0.850 ns) = 0.850 ns; Loc. = PIN_63; Fanout = 1; PIN Node = 'keyin0'
        Info: 2: + IC(5.518 ns) + CELL(0.149 ns) = 6.517 ns; Loc. = LCCOMB_X17_Y11_N8; Fanout = 1; COMB Node = 'keycod[0]~reg0feeder'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.601 ns; Loc. = LCFF_X17_Y11_N9; Fanout = 1; REG Node = 'keycod[0]~reg0'
        Info: Total cell delay = 1.083 ns ( 16.41 % )
        Info: Total interconnect delay = 5.518 ns ( 83.59 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "rst"