series.vhd

FPGA实验：用于检测输入的二进制系列

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity series is
    port(
        rst:in    std_logic;---开关接sw_17
        clk:in    std_logic;---晶振
		keyin0:in    std_logic;
		keyin1:in    std_logic;
		keyin2:in    std_logic;
		keyin3:in    std_logic;
		keyin4:in    std_logic;
		keyin5:in    std_logic;
		keyin6:in    std_logic;
		keyin7:in    std_logic;
		keyin8:in    std_logic;
		keyin9:in    std_logic;
		keyin10:in    std_logic;
		keyin11:in    std_logic;
		keyin12:in    std_logic;
		keyin13:in    std_logic;
		keyin14:in    std_logic;
		keyin15:in    std_logic;
		keyin16:in    std_logic;
		clk0:out   std_logic;--1Hz的时钟
		clk1:out   std_logic;--1KHz的时钟
		keycod:out	  std_logic_vector(16 downto 0)--输出的键代码
    );
end series;

architecture series_arch of series is
	signal clkfrq0	 :    std_logic;
    signal cntfrq0   :    std_logic_vector(14 downto 0);
	signal clkfrq1	 :    std_logic;
    signal cntfrq1   :    std_logic_vector(14 downto 0);

begin
    process(rst,clk) --产生1Hz时钟
    begin
        if rst = '1' then
            clkfrq0<= '0';
            cntfrq0 <= "000000000000000";
        elsif clk'event and clk = '1' then
            if cntfrq0 = "000000000010000" then ----"110000110101000"分频
                cntfrq0 <= "000000000000000";
				clkfrq0<=not clkfrq0;
                clk0 <= clkfrq0;
            else
                cntfrq0 <= cntfrq0 + 1;
            end if;
        end if;
    end process;
  
	 process(rst,clk) --产生1KHz时钟
    begin
        if rst = '1' then
            clkfrq1<= '0';
            cntfrq1 <= "000000000000000";
        elsif clk'event and clk = '1' then
            if cntfrq1 = "000000000000010" then ----"110000110101000"分频
                cntfrq1 <= "000000000000000";
				clkfrq1<=not clkfrq1;
                clk1 <= clkfrq1;
            else
                cntfrq1 <= cntfrq1 + 1;
            end if;
        end if;
    end process;
    process --当开关闭合时将此时的系列输入,开关打开时将"0101010101010101"作为系列
    --variable key:std_logic_vector(16 downto 0);
	begin
       	wait until rst'event and rst = '0';
            keycod<=keyin16&keyin15&keyin14&keyin13&keyin12&keyin11&keyin10&keyin9&keyin8&keyin7&keyin6&keyin5&keyin4&keyin3&keyin2&keyin1&keyin0;
    end process;
    
end series_arch;