series_detection.tan.qmsg

FPGA实验：用于检测输入的二进制系列

{ "Info" "ITDB_TH_RESULT" "series:inst\|keycod\[11\] key11 rst 4.521 ns register " "Info: th for register \"series:inst\|keycod\[11\]\" (data pin = \"key11\", clock pin = \"rst\") is 4.521 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "rst destination 6.909 ns + Longest register " "Info: + Longest clock path from clock \"rst\" to destination register is 6.909 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns rst 1 CLK PIN_V2 70 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V2; Fanout = 70; CLK Node = 'rst'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "series_detection.bdf" "" { Schematic "E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.bdf" { { 88 104 272 104 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.520 ns) + CELL(0.537 ns) 6.909 ns series:inst\|keycod\[11\] 2 REG LCFF_X15_Y14_N23 1 " "Info: 2: + IC(5.520 ns) + CELL(0.537 ns) = 6.909 ns; Loc. = LCFF_X15_Y14_N23; Fanout = 1; REG Node = 'series:inst\|keycod\[11\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.057 ns" { rst series:inst|keycod[11] } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.389 ns ( 20.10 % ) " "Info: Total cell delay = 1.389 ns ( 20.10 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.520 ns ( 79.90 % ) " "Info: Total interconnect delay = 5.520 ns ( 79.90 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.909 ns" { rst series:inst|keycod[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.909 ns" { rst rst~combout series:inst|keycod[11] } { 0.000ns 0.000ns 5.520ns } { 0.000ns 0.852ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TH_DELAY" "0.266 ns + " "Info: + Micro hold delay of destination is 0.266 ns" {  } { { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 75 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.654 ns - Shortest pin register " "Info: - Shortest pin to register delay is 2.654 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns key11 1 PIN PIN_P1 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_P1; Fanout = 1; PIN Node = 'key11'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { key11 } "NODE_NAME" } } { "series_detection.bdf" "" { Schematic "E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.bdf" { { 296 104 272 312 "key11" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.289 ns) + CELL(0.366 ns) 2.654 ns series:inst\|keycod\[11\] 2 REG LCFF_X15_Y14_N23 1 " "Info: 2: + IC(1.289 ns) + CELL(0.366 ns) = 2.654 ns; Loc. = LCFF_X15_Y14_N23; Fanout = 1; REG Node = 'series:inst\|keycod\[11\]'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.655 ns" { key11 series:inst|keycod[11] } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 75 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.365 ns ( 51.43 % ) " "Info: Total cell delay = 1.365 ns ( 51.43 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.289 ns ( 48.57 % ) " "Info: Total interconnect delay = 1.289 ns ( 48.57 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.654 ns" { key11 series:inst|keycod[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.654 ns" { key11 key11~combout series:inst|keycod[11] } { 0.000ns 0.000ns 1.289ns } { 0.000ns 0.999ns 0.366ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.909 ns" { rst series:inst|keycod[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.909 ns" { rst rst~combout series:inst|keycod[11] } { 0.000ns 0.000ns 5.520ns } { 0.000ns 0.852ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.654 ns" { key11 series:inst|keycod[11] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.654 ns" { key11 key11~combout series:inst|keycod[11] } { 0.000ns 0.000ns 1.289ns } { 0.000ns 0.999ns 0.366ns } } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Fri Oct 31 15:20:49 2008 " "Info: Processing ended: Fri Oct 31 15:20:49 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}