series_detection.tan.qmsg

FPGA实验：用于检测输入的二进制系列

{ "Info" "ITAN_NO_REG2REG_EXIST" "rst " "Info: No valid register-to-register data paths exist for clock \"rst\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0}
{ "Info" "ITDB_TSU_RESULT" "series:inst\|clk0 rst clk 4.596 ns register " "Info: tsu for register \"series:inst\|clk0\" (data pin = \"rst\", clock pin = \"clk\") is 4.596 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.309 ns + Longest pin register " "Info: + Longest pin to register delay is 7.309 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.852 ns) 0.852 ns rst 1 CLK PIN_V2 70 " "Info: 1: + IC(0.000 ns) + CELL(0.852 ns) = 0.852 ns; Loc. = PIN_V2; Fanout = 70; CLK Node = 'rst'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { rst } "NODE_NAME" } } { "series_detection.bdf" "" { Schematic "E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.bdf" { { 88 104 272 104 "rst" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(5.935 ns) + CELL(0.438 ns) 7.225 ns series:inst\|clk0~64 2 COMB LCCOMB_X18_Y15_N4 1 " "Info: 2: + IC(5.935 ns) + CELL(0.438 ns) = 7.225 ns; Loc. = LCCOMB_X18_Y15_N4; Fanout = 1; COMB Node = 'series:inst\|clk0~64'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.373 ns" { rst series:inst|clk0~64 } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 7.309 ns series:inst\|clk0 3 REG LCFF_X18_Y15_N5 2 " "Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 7.309 ns; Loc. = LCFF_X18_Y15_N5; Fanout = 2; REG Node = 'series:inst\|clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { series:inst|clk0~64 series:inst|clk0 } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.374 ns ( 18.80 % ) " "Info: Total cell delay = 1.374 ns ( 18.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "5.935 ns ( 81.20 % ) " "Info: Total interconnect delay = 5.935 ns ( 81.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.309 ns" { rst series:inst|clk0~64 series:inst|clk0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.309 ns" { rst rst~combout series:inst|clk0~64 series:inst|clk0 } { 0.000ns 0.000ns 5.935ns 0.000ns } { 0.000ns 0.852ns 0.438ns 0.084ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" {  } { { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 26 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.677 ns - Shortest register " "Info: - Shortest clock path from clock \"clk\" to destination register is 2.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "series_detection.bdf" "" { Schematic "E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.bdf" { { 104 104 272 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 44 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 44; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "series_detection.bdf" "" { Schematic "E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.bdf" { { 104 104 272 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.537 ns) 2.677 ns series:inst\|clk0 3 REG LCFF_X18_Y15_N5 2 " "Info: 3: + IC(1.023 ns) + CELL(0.537 ns) = 2.677 ns; Loc. = LCFF_X18_Y15_N5; Fanout = 2; REG Node = 'series:inst\|clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.560 ns" { clk~clkctrl series:inst|clk0 } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.38 % ) " "Info: Total cell delay = 1.536 ns ( 57.38 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.141 ns ( 42.62 % ) " "Info: Total interconnect delay = 1.141 ns ( 42.62 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.677 ns" { clk clk~clkctrl series:inst|clk0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.677 ns" { clk clk~combout clk~clkctrl series:inst|clk0 } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "7.309 ns" { rst series:inst|clk0~64 series:inst|clk0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "7.309 ns" { rst rst~combout series:inst|clk0~64 series:inst|clk0 } { 0.000ns 0.000ns 5.935ns 0.000ns } { 0.000ns 0.852ns 0.438ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.677 ns" { clk clk~clkctrl series:inst|clk0 } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.677 ns" { clk clk~combout clk~clkctrl series:inst|clk0 } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk z state:inst1\|z 12.208 ns register " "Info: tco from clock \"clk\" to destination pin \"z\" through register \"state:inst1\|z\" is 12.208 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 6.679 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 6.679 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "series_detection.bdf" "" { Schematic "E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.bdf" { { 104 104 272 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 44 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 44; COMB Node = 'clk~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "series_detection.bdf" "" { Schematic "E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.bdf" { { 104 104 272 120 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.787 ns) 2.927 ns series:inst\|clk0 3 REG LCFF_X18_Y15_N5 2 " "Info: 3: + IC(1.023 ns) + CELL(0.787 ns) = 2.927 ns; Loc. = LCFF_X18_Y15_N5; Fanout = 2; REG Node = 'series:inst\|clk0'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.810 ns" { clk~clkctrl series:inst|clk0 } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.189 ns) + CELL(0.000 ns) 5.116 ns series:inst\|clk0~clkctrl 4 COMB CLKCTRL_G13 14 " "Info: 4: + IC(2.189 ns) + CELL(0.000 ns) = 5.116 ns; Loc. = CLKCTRL_G13; Fanout = 14; COMB Node = 'series:inst\|clk0~clkctrl'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.189 ns" { series:inst|clk0 series:inst|clk0~clkctrl } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.026 ns) + CELL(0.537 ns) 6.679 ns state:inst1\|z 5 REG LCFF_X14_Y12_N23 3 " "Info: 5: + IC(1.026 ns) + CELL(0.537 ns) = 6.679 ns; Loc. = LCFF_X14_Y12_N23; Fanout = 3; REG Node = 'state:inst1\|z'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.563 ns" { series:inst|clk0~clkctrl state:inst1|z } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/state.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.323 ns ( 34.78 % ) " "Info: Total cell delay = 2.323 ns ( 34.78 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.356 ns ( 65.22 % ) " "Info: Total interconnect delay = 4.356 ns ( 65.22 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.679 ns" { clk clk~clkctrl series:inst|clk0 series:inst|clk0~clkctrl state:inst1|z } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.679 ns" { clk clk~combout clk~clkctrl series:inst|clk0 series:inst|clk0~clkctrl state:inst1|z } { 0.000ns 0.000ns 0.118ns 1.023ns 2.189ns 1.026ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" {  } { { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/state.vhd" 7 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.279 ns + Longest register pin " "Info: + Longest register to pin delay is 5.279 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state:inst1\|z 1 REG LCFF_X14_Y12_N23 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X14_Y12_N23; Fanout = 3; REG Node = 'state:inst1\|z'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { state:inst1|z } "NODE_NAME" } } { "state.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/state.vhd" 7 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(2.481 ns) + CELL(2.798 ns) 5.279 ns z 2 PIN PIN_AD12 0 " "Info: 2: + IC(2.481 ns) + CELL(2.798 ns) = 5.279 ns; Loc. = PIN_AD12; Fanout = 0; PIN Node = 'z'" {  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.279 ns" { state:inst1|z z } "NODE_NAME" } } { "series_detection.bdf" "" { Schematic "E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.bdf" { { 72 656 832 88 "z" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.798 ns ( 53.00 % ) " "Info: Total cell delay = 2.798 ns ( 53.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.481 ns ( 47.00 % ) " "Info: Total interconnect delay = 2.481 ns ( 47.00 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.279 ns" { state:inst1|z z } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.279 ns" { state:inst1|z z } { 0.000ns 2.481ns } { 0.000ns 2.798ns } } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0}  } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "6.679 ns" { clk clk~clkctrl series:inst|clk0 series:inst|clk0~clkctrl state:inst1|z } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "6.679 ns" { clk clk~combout clk~clkctrl series:inst|clk0 series:inst|clk0~clkctrl state:inst1|z } { 0.000ns 0.000ns 0.118ns 1.023ns 2.189ns 1.026ns } { 0.000ns 0.999ns 0.000ns 0.787ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "5.279 ns" { state:inst1|z z } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "5.279 ns" { state:inst1|z z } { 0.000ns 2.481ns } { 0.000ns 2.798ns } } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0}