📄 series_detection.tan.qmsg
字号:
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" { } { { "series_detection.bdf" "" { Schematic "E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.bdf" { { 104 104 272 120 "clk" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "clk" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "rst " "Info: Assuming node \"rst\" is an undefined clock" { } { { "series_detection.bdf" "" { Schematic "E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.bdf" { { 88 104 272 104 "rst" "" } } } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "rst" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "series:inst\|clk1 " "Info: Detected ripple clock \"series:inst\|clk1\" as buffer" { } { { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 27 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "series:inst\|clk1" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} { "Info" "ITAN_RIPPLE_CLK" "series:inst\|clk0 " "Info: Detected ripple clock \"series:inst\|clk0\" as buffer" { } { { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 26 -1 0 } } { "c:/altera/quartus60/win/Assignment Editor.qase" "" { Assignment "c:/altera/quartus60/win/Assignment Editor.qase" 1 { { 0 "series:inst\|clk0" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register series:inst\|cntfrq0\[0\] register series:inst\|cntfrq0\[24\] 223.66 MHz 4.471 ns Internal " "Info: Clock \"clk\" has Internal fmax of 223.66 MHz between source register \"series:inst\|cntfrq0\[0\]\" and destination register \"series:inst\|cntfrq0\[24\]\" (period= 4.471 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.257 ns + Longest register register " "Info: + Longest register to register delay is 4.257 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns series:inst\|cntfrq0\[0\] 1 REG LCFF_X18_Y15_N15 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X18_Y15_N15; Fanout = 3; REG Node = 'series:inst\|cntfrq0\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { series:inst|cntfrq0[0] } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.470 ns) + CELL(0.414 ns) 0.884 ns series:inst\|Add0~301 2 COMB LCCOMB_X19_Y15_N8 2 " "Info: 2: + IC(0.470 ns) + CELL(0.414 ns) = 0.884 ns; Loc. = LCCOMB_X19_Y15_N8; Fanout = 2; COMB Node = 'series:inst\|Add0~301'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.884 ns" { series:inst|cntfrq0[0] series:inst|Add0~301 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 0.955 ns series:inst\|Add0~303 3 COMB LCCOMB_X19_Y15_N10 2 " "Info: 3: + IC(0.000 ns) + CELL(0.071 ns) = 0.955 ns; Loc. = LCCOMB_X19_Y15_N10; Fanout = 2; COMB Node = 'series:inst\|Add0~303'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~301 series:inst|Add0~303 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.026 ns series:inst\|Add0~305 4 COMB LCCOMB_X19_Y15_N12 2 " "Info: 4: + IC(0.000 ns) + CELL(0.071 ns) = 1.026 ns; Loc. = LCCOMB_X19_Y15_N12; Fanout = 2; COMB Node = 'series:inst\|Add0~305'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~303 series:inst|Add0~305 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 1.185 ns series:inst\|Add0~307 5 COMB LCCOMB_X19_Y15_N14 2 " "Info: 5: + IC(0.000 ns) + CELL(0.159 ns) = 1.185 ns; Loc. = LCCOMB_X19_Y15_N14; Fanout = 2; COMB Node = 'series:inst\|Add0~307'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { series:inst|Add0~305 series:inst|Add0~307 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.256 ns series:inst\|Add0~309 6 COMB LCCOMB_X19_Y15_N16 2 " "Info: 6: + IC(0.000 ns) + CELL(0.071 ns) = 1.256 ns; Loc. = LCCOMB_X19_Y15_N16; Fanout = 2; COMB Node = 'series:inst\|Add0~309'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~307 series:inst|Add0~309 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.327 ns series:inst\|Add0~311 7 COMB LCCOMB_X19_Y15_N18 2 " "Info: 7: + IC(0.000 ns) + CELL(0.071 ns) = 1.327 ns; Loc. = LCCOMB_X19_Y15_N18; Fanout = 2; COMB Node = 'series:inst\|Add0~311'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~309 series:inst|Add0~311 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.398 ns series:inst\|Add0~313 8 COMB LCCOMB_X19_Y15_N20 2 " "Info: 8: + IC(0.000 ns) + CELL(0.071 ns) = 1.398 ns; Loc. = LCCOMB_X19_Y15_N20; Fanout = 2; COMB Node = 'series:inst\|Add0~313'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~311 series:inst|Add0~313 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.469 ns series:inst\|Add0~315 9 COMB LCCOMB_X19_Y15_N22 2 " "Info: 9: + IC(0.000 ns) + CELL(0.071 ns) = 1.469 ns; Loc. = LCCOMB_X19_Y15_N22; Fanout = 2; COMB Node = 'series:inst\|Add0~315'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~313 series:inst|Add0~315 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.540 ns series:inst\|Add0~317 10 COMB LCCOMB_X19_Y15_N24 2 " "Info: 10: + IC(0.000 ns) + CELL(0.071 ns) = 1.540 ns; Loc. = LCCOMB_X19_Y15_N24; Fanout = 2; COMB Node = 'series:inst\|Add0~317'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~315 series:inst|Add0~317 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.611 ns series:inst\|Add0~319 11 COMB LCCOMB_X19_Y15_N26 2 " "Info: 11: + IC(0.000 ns) + CELL(0.071 ns) = 1.611 ns; Loc. = LCCOMB_X19_Y15_N26; Fanout = 2; COMB Node = 'series:inst\|Add0~319'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~317 series:inst|Add0~319 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.682 ns series:inst\|Add0~321 12 COMB LCCOMB_X19_Y15_N28 2 " "Info: 12: + IC(0.000 ns) + CELL(0.071 ns) = 1.682 ns; Loc. = LCCOMB_X19_Y15_N28; Fanout = 2; COMB Node = 'series:inst\|Add0~321'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~319 series:inst|Add0~321 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.146 ns) 1.828 ns series:inst\|Add0~323 13 COMB LCCOMB_X19_Y15_N30 2 " "Info: 13: + IC(0.000 ns) + CELL(0.146 ns) = 1.828 ns; Loc. = LCCOMB_X19_Y15_N30; Fanout = 2; COMB Node = 'series:inst\|Add0~323'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.146 ns" { series:inst|Add0~321 series:inst|Add0~323 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.899 ns series:inst\|Add0~325 14 COMB LCCOMB_X19_Y14_N0 2 " "Info: 14: + IC(0.000 ns) + CELL(0.071 ns) = 1.899 ns; Loc. = LCCOMB_X19_Y14_N0; Fanout = 2; COMB Node = 'series:inst\|Add0~325'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~323 series:inst|Add0~325 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 1.970 ns series:inst\|Add0~327 15 COMB LCCOMB_X19_Y14_N2 2 " "Info: 15: + IC(0.000 ns) + CELL(0.071 ns) = 1.970 ns; Loc. = LCCOMB_X19_Y14_N2; Fanout = 2; COMB Node = 'series:inst\|Add0~327'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~325 series:inst|Add0~327 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.041 ns series:inst\|Add0~329 16 COMB LCCOMB_X19_Y14_N4 2 " "Info: 16: + IC(0.000 ns) + CELL(0.071 ns) = 2.041 ns; Loc. = LCCOMB_X19_Y14_N4; Fanout = 2; COMB Node = 'series:inst\|Add0~329'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~327 series:inst|Add0~329 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.112 ns series:inst\|Add0~331 17 COMB LCCOMB_X19_Y14_N6 2 " "Info: 17: + IC(0.000 ns) + CELL(0.071 ns) = 2.112 ns; Loc. = LCCOMB_X19_Y14_N6; Fanout = 2; COMB Node = 'series:inst\|Add0~331'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~329 series:inst|Add0~331 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.183 ns series:inst\|Add0~333 18 COMB LCCOMB_X19_Y14_N8 2 " "Info: 18: + IC(0.000 ns) + CELL(0.071 ns) = 2.183 ns; Loc. = LCCOMB_X19_Y14_N8; Fanout = 2; COMB Node = 'series:inst\|Add0~333'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~331 series:inst|Add0~333 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.254 ns series:inst\|Add0~335 19 COMB LCCOMB_X19_Y14_N10 2 " "Info: 19: + IC(0.000 ns) + CELL(0.071 ns) = 2.254 ns; Loc. = LCCOMB_X19_Y14_N10; Fanout = 2; COMB Node = 'series:inst\|Add0~335'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~333 series:inst|Add0~335 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.325 ns series:inst\|Add0~337 20 COMB LCCOMB_X19_Y14_N12 2 " "Info: 20: + IC(0.000 ns) + CELL(0.071 ns) = 2.325 ns; Loc. = LCCOMB_X19_Y14_N12; Fanout = 2; COMB Node = 'series:inst\|Add0~337'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~335 series:inst|Add0~337 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.159 ns) 2.484 ns series:inst\|Add0~339 21 COMB LCCOMB_X19_Y14_N14 2 " "Info: 21: + IC(0.000 ns) + CELL(0.159 ns) = 2.484 ns; Loc. = LCCOMB_X19_Y14_N14; Fanout = 2; COMB Node = 'series:inst\|Add0~339'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.159 ns" { series:inst|Add0~337 series:inst|Add0~339 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.555 ns series:inst\|Add0~341 22 COMB LCCOMB_X19_Y14_N16 2 " "Info: 22: + IC(0.000 ns) + CELL(0.071 ns) = 2.555 ns; Loc. = LCCOMB_X19_Y14_N16; Fanout = 2; COMB Node = 'series:inst\|Add0~341'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~339 series:inst|Add0~341 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.626 ns series:inst\|Add0~343 23 COMB LCCOMB_X19_Y14_N18 2 " "Info: 23: + IC(0.000 ns) + CELL(0.071 ns) = 2.626 ns; Loc. = LCCOMB_X19_Y14_N18; Fanout = 2; COMB Node = 'series:inst\|Add0~343'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~341 series:inst|Add0~343 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.697 ns series:inst\|Add0~345 24 COMB LCCOMB_X19_Y14_N20 2 " "Info: 24: + IC(0.000 ns) + CELL(0.071 ns) = 2.697 ns; Loc. = LCCOMB_X19_Y14_N20; Fanout = 2; COMB Node = 'series:inst\|Add0~345'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~343 series:inst|Add0~345 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.071 ns) 2.768 ns series:inst\|Add0~347 25 COMB LCCOMB_X19_Y14_N22 1 " "Info: 25: + IC(0.000 ns) + CELL(0.071 ns) = 2.768 ns; Loc. = LCCOMB_X19_Y14_N22; Fanout = 1; COMB Node = 'series:inst\|Add0~347'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.071 ns" { series:inst|Add0~345 series:inst|Add0~347 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.410 ns) 3.178 ns series:inst\|Add0~348 26 COMB LCCOMB_X19_Y14_N24 1 " "Info: 26: + IC(0.000 ns) + CELL(0.410 ns) = 3.178 ns; Loc. = LCCOMB_X19_Y14_N24; Fanout = 1; COMB Node = 'series:inst\|Add0~348'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.410 ns" { series:inst|Add0~347 series:inst|Add0~348 } "NODE_NAME" } } { "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" "" { Text "c:/altera/quartus60/libraries/vhdl/synopsys/syn_unsi.vhd" 117 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.720 ns) + CELL(0.275 ns) 4.173 ns series:inst\|cntfrq0~240 27 COMB LCCOMB_X18_Y15_N18 1 " "Info: 27: + IC(0.720 ns) + CELL(0.275 ns) = 4.173 ns; Loc. = LCCOMB_X18_Y15_N18; Fanout = 1; COMB Node = 'series:inst\|cntfrq0~240'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.995 ns" { series:inst|Add0~348 series:inst|cntfrq0~240 } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 34 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 4.257 ns series:inst\|cntfrq0\[24\] 28 REG LCFF_X18_Y15_N19 2 " "Info: 28: + IC(0.000 ns) + CELL(0.084 ns) = 4.257 ns; Loc. = LCFF_X18_Y15_N19; Fanout = 2; REG Node = 'series:inst\|cntfrq0\[24\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.084 ns" { series:inst|cntfrq0~240 series:inst|cntfrq0[24] } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.067 ns ( 72.05 % ) " "Info: Total cell delay = 3.067 ns ( 72.05 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.190 ns ( 27.95 % ) " "Info: Total interconnect delay = 1.190 ns ( 27.95 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.257 ns" { series:inst|cntfrq0[0] series:inst|Add0~301 series:inst|Add0~303 series:inst|Add0~305 series:inst|Add0~307 series:inst|Add0~309 series:inst|Add0~311 series:inst|Add0~313 series:inst|Add0~315 series:inst|Add0~317 series:inst|Add0~319 series:inst|Add0~321 series:inst|Add0~323 series:inst|Add0~325 series:inst|Add0~327 series:inst|Add0~329 series:inst|Add0~331 series:inst|Add0~333 series:inst|Add0~335 series:inst|Add0~337 series:inst|Add0~339 series:inst|Add0~341 series:inst|Add0~343 series:inst|Add0~345 series:inst|Add0~347 series:inst|Add0~348 series:inst|cntfrq0~240 series:inst|cntfrq0[24] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.257 ns" { series:inst|cntfrq0[0] series:inst|Add0~301 series:inst|Add0~303 series:inst|Add0~305 series:inst|Add0~307 series:inst|Add0~309 series:inst|Add0~311 series:inst|Add0~313 series:inst|Add0~315 series:inst|Add0~317 series:inst|Add0~319 series:inst|Add0~321 series:inst|Add0~323 series:inst|Add0~325 series:inst|Add0~327 series:inst|Add0~329 series:inst|Add0~331 series:inst|Add0~333 series:inst|Add0~335 series:inst|Add0~337 series:inst|Add0~339 series:inst|Add0~341 series:inst|Add0~343 series:inst|Add0~345 series:inst|Add0~347 series:inst|Add0~348 series:inst|cntfrq0~240 series:inst|cntfrq0[24] } { 0.000ns 0.470ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.720ns 0.000ns } { 0.000ns 0.414ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.275ns 0.084ns } } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.677 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "series_detection.bdf" "" { Schematic "E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.bdf" { { 104 104 272 120 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 44 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 44; COMB Node = 'clk~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "series_detection.bdf" "" { Schematic "E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.bdf" { { 104 104 272 120 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.537 ns) 2.677 ns series:inst\|cntfrq0\[24\] 3 REG LCFF_X18_Y15_N19 2 " "Info: 3: + IC(1.023 ns) + CELL(0.537 ns) = 2.677 ns; Loc. = LCFF_X18_Y15_N19; Fanout = 2; REG Node = 'series:inst\|cntfrq0\[24\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.560 ns" { clk~clkctrl series:inst|cntfrq0[24] } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.38 % ) " "Info: Total cell delay = 1.536 ns ( 57.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.141 ns ( 42.62 % ) " "Info: Total interconnect delay = 1.141 ns ( 42.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.677 ns" { clk clk~clkctrl series:inst|cntfrq0[24] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.677 ns" { clk clk~combout clk~clkctrl series:inst|cntfrq0[24] } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.677 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.677 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.999 ns) 0.999 ns clk 1 CLK PIN_N2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 1; CLK Node = 'clk'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "series_detection.bdf" "" { Schematic "E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.bdf" { { 104 104 272 120 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.118 ns) + CELL(0.000 ns) 1.117 ns clk~clkctrl 2 COMB CLKCTRL_G2 44 " "Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 44; COMB Node = 'clk~clkctrl'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "0.118 ns" { clk clk~clkctrl } "NODE_NAME" } } { "series_detection.bdf" "" { Schematic "E:/lessons/电路与系统/实验设计/实验/series_detection/series_detection.bdf" { { 104 104 272 120 "clk" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(1.023 ns) + CELL(0.537 ns) 2.677 ns series:inst\|cntfrq0\[0\] 3 REG LCFF_X18_Y15_N15 3 " "Info: 3: + IC(1.023 ns) + CELL(0.537 ns) = 2.677 ns; Loc. = LCFF_X18_Y15_N15; Fanout = 3; REG Node = 'series:inst\|cntfrq0\[0\]'" { } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "1.560 ns" { clk~clkctrl series:inst|cntfrq0[0] } "NODE_NAME" } } { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 41 -1 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.536 ns ( 57.38 % ) " "Info: Total cell delay = 1.536 ns ( 57.38 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.141 ns ( 42.62 % ) " "Info: Total interconnect delay = 1.141 ns ( 42.62 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.677 ns" { clk clk~clkctrl series:inst|cntfrq0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.677 ns" { clk clk~combout clk~clkctrl series:inst|cntfrq0[0] } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.677 ns" { clk clk~clkctrl series:inst|cntfrq0[24] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.677 ns" { clk clk~combout clk~clkctrl series:inst|cntfrq0[24] } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.677 ns" { clk clk~clkctrl series:inst|cntfrq0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.677 ns" { clk clk~combout clk~clkctrl series:inst|cntfrq0[0] } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns + " "Info: + Micro clock to output delay of source is 0.250 ns" { } { { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 41 -1 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns + " "Info: + Micro setup delay of destination is -0.036 ns" { } { { "series.vhd" "" { Text "E:/lessons/电路与系统/实验设计/实验/series_detection/series.vhd" 41 -1 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0} } { { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "4.257 ns" { series:inst|cntfrq0[0] series:inst|Add0~301 series:inst|Add0~303 series:inst|Add0~305 series:inst|Add0~307 series:inst|Add0~309 series:inst|Add0~311 series:inst|Add0~313 series:inst|Add0~315 series:inst|Add0~317 series:inst|Add0~319 series:inst|Add0~321 series:inst|Add0~323 series:inst|Add0~325 series:inst|Add0~327 series:inst|Add0~329 series:inst|Add0~331 series:inst|Add0~333 series:inst|Add0~335 series:inst|Add0~337 series:inst|Add0~339 series:inst|Add0~341 series:inst|Add0~343 series:inst|Add0~345 series:inst|Add0~347 series:inst|Add0~348 series:inst|cntfrq0~240 series:inst|cntfrq0[24] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "4.257 ns" { series:inst|cntfrq0[0] series:inst|Add0~301 series:inst|Add0~303 series:inst|Add0~305 series:inst|Add0~307 series:inst|Add0~309 series:inst|Add0~311 series:inst|Add0~313 series:inst|Add0~315 series:inst|Add0~317 series:inst|Add0~319 series:inst|Add0~321 series:inst|Add0~323 series:inst|Add0~325 series:inst|Add0~327 series:inst|Add0~329 series:inst|Add0~331 series:inst|Add0~333 series:inst|Add0~335 series:inst|Add0~337 series:inst|Add0~339 series:inst|Add0~341 series:inst|Add0~343 series:inst|Add0~345 series:inst|Add0~347 series:inst|Add0~348 series:inst|cntfrq0~240 series:inst|cntfrq0[24] } { 0.000ns 0.470ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.720ns 0.000ns } { 0.000ns 0.414ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.146ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.071ns 0.159ns 0.071ns 0.071ns 0.071ns 0.071ns 0.410ns 0.275ns 0.084ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.677 ns" { clk clk~clkctrl series:inst|cntfrq0[24] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.677 ns" { clk clk~combout clk~clkctrl series:inst|cntfrq0[24] } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } { "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/quartus60/win/TimingClosureFloorplan.fld" "" "2.677 ns" { clk clk~clkctrl series:inst|cntfrq0[0] } "NODE_NAME" } } { "c:/altera/quartus60/win/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus60/win/Technology_Viewer.qrui" "2.677 ns" { clk clk~combout clk~clkctrl series:inst|cntfrq0[0] } { 0.000ns 0.000ns 0.118ns 1.023ns } { 0.000ns 0.999ns 0.000ns 0.537ns } } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0}
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