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《数字电路EDA入门－VHDL程序实例》---数字秒表程序例子

《数字电路EDA入门－VHDL程序实例》---数字秒表程序例子 
2005-8-27 

程序说明：1。此程序包括分频，计数控制，显示控制部分。
2。开机显示00。00。00，用户课随时计时，暂停，清零，最大计时可到59 分59。99秒。
3。技术时钟为100HZ
4。采用时分复用的方法控制4个数码管的显示，可节省资源。
程序如下：
Library ieee;
Use ieee.std_logic_1164.all;
Use ieee.std_logic_arith.all; 
Use ieee.std_logic_unsigned.all;
Entity watch is
Port(sel: out std_logic_vector(6 downto 1) ;
seg:out std_logic_vector(7 downto 0);
Beginstop:in std_logic;
Reset:in std_logic;
Cp2:in std_logic);
End watch;
Architecture behave of watch is
Signal num1: std_logic_vector(3 downto 0);
Signal num2: std_logic_vector(3 downto 0);
Signal num3: std_logic_vector(3 downto 0);
Signal num4: std_logic_vector(3 downto 0);
Signal num5: std_logic_vector(3 downto 0);
Signal num6: std_logic_vector(3 downto 0);
Signal num: std_logic_vector(3 downto 0);
Signal numlet: std_logic_vector(2 downto 0);
Signal count: std_logic_vector(17 downto 1);
Signal selsig: std_logic_vector(6 downto 1);
Signal segsig: std_logic_vector(7 downto 0 );
Signal cp1: std_logic;
Signal cp3: std_logic;
Begin
Process(cp2) ---- 分频。
Begin 
If (cp2' event and cp2='1') then 
if (Count="1100011010011111")then
count<="00000000000000000"; cp1<=not cp1;
else count<=count 1;
end if;
end if;
cp3<=count(10);
end process;
process(cp1)
begin 
if reset ='1' then num1(3 downto 0) <="0000";
num2(3 downto 0) <="0000";
num3(3 downto 0) <="0000";
num4(3 downto 0) <="0000";
num5(3 downto 0) <="0000";
num6(3 downto 0) <="0000";

else if cp1' event and cp1='1' then 
if beginstop='1' then num1<=num1 1;
if num1 (3 downto 0)="1001" then 
num1 (3 downto 0)<="0000"; num2<= num2 1;
if num2 (3 downto 0)="1001" then 
num2 (3 downto 0)<="0000"; num3<= num3 1;
if num3 (3 downto 0)="1001" then 
num3 (3 downto 0)<="0000"; num4<= num4 1;
if num4 (3 downto 0)="0101" then 
num4 (3 downto 0)<="0000"; num5<= num5 1;
if num5 (3 downto 0)="1001" then 
num5 (3 downto 0)<="0000"; num6<= num6 1;
if num6 (3 downto 0)="0101" then 
num6(3 downto 0)<="0000";
end if; end if; end if; end if; end if; end if; end if;
end if; end if;
end process;
process (cp3) 
begin 
if (cp3' event and cp3='1')then 
if(numlet(2 downto 0)="000") then
num<=num1;selsig(6 downto 1)<="111110"; end if;
if(numlet(2 downto 0)="001") then
num<=num2;selsig(6 downto 1)<="111101"; end if;
if(numlet(2 downto 0)="010") then
num<=num3;selsig(6 downto 1)<="111011"; end if;
if(numlet(2 downto 0)="011") then
num<=num4;selsig(6 downto 1)<="110111"; end if;
if(numlet(2 downto 0)="100") then
num<=num5;selsig(6 downto 1)<="101111"; end if;
numlet(2 downto 0)<=numlet(2 downto 0) 1;
if(numlet(2 downto 0)="101") then
numlet(2 downto 0)<="011111"; end if;
end if;
if (num (3 downto 0)="0000")then 
segsig(7 downto 0)<="01111111"; end if;
if (num (3 downto 0)="0001")then 
segsig(7 downto 0)<="00001101"; end if;
if (num (3 downto 0)="0010")then 
segsig(7 downto 0)<="10110111"; end if;
if (num (3 downto 0)="0011")then 
segsig(7 downto 0)<="10011111"; end if;
if (num (3 downto 0)="0100")then 
segsig(7 downto 0)<="11001101"; end if;
if (num (3 downto 0)="0101")then 
segsig(7 downto 0)<="11011011"; end if;
if (num (3 downto 0)="0110")then 
segsig(7 downto 0)<="11111011"; end if;
if (num (3 downto 0)="0111")then 
segsig(7 downto 0)<="00001111"; end if;
if (num (3 downto 0)="1000")then 
segsig(7 downto 0)<="11111111"; end if;
if (num (3 downto 0)="1001")then 
segsig(7 downto 0)<="11011111"; end if;
end process;
sel<=selsig;
seg(7 downto 0)<=segsig(7 downto 0);
end behave;