alarmclk.abv

这是一个非常好的VHDL的源码

module alarmclk

clock,reset	pin;
new_clk_time_0_,new_clk_time_1_,new_clk_time_2_,new_clk_time_3_	pin;
ld_new_clk_time		pin;
showalrm	pin;
new_alrm_time_0_,new_alrm_time_1_,new_alrm_time_2_,new_alrm_time_3_	pin;
ld_new_alrm_time	pin;
dummy		pin;


new_clk = [new_clk_time_3_,new_clk_time_2_,new_clk_time_1_,new_clk_time_0_];
new_alrm = [new_alrm_time_3_,new_alrm_time_2_,new_alrm_time_1_,new_alrm_time_0_];

test_vectors

([clock,ld_new_alrm_time,ld_new_clk_time,new_alrm,new_clk,reset,showalrm] -> [dummy]);

[.x.,0,0,0,0,1,0]	->	[.x.];
[.c.,0,0,0,0,0,0]	->	[.x.];
[.c.,0,0,0,0,0,0]	->	[.x.];
[.c.,0,0,0,0,0,0]	->	[.x.];
[.c.,0,0,0,0,0,0]	->	[.x.];
[.c.,0,0,0,0,0,0]	->	[.x.];
[.c.,1,0,^hb,0,0,0]	->	[.x.];
[.c.,0,0,^hb,0,0,1]	->	[.x.];
[.c.,0,0,^hb,0,0,0]	->	[.x.];
[.c.,0,0,^hb,0,0,0]	->	[.x.];
[.c.,0,0,^hb,0,0,0]	->	[.x.];
[.c.,0,0,^hb,0,0,0]	->	[.x.];
[.c.,0,0,^hb,0,0,0]	->	[.x.];
[.c.,0,0,^hb,0,0,0]	->	[.x.];
[.c.,0,0,^hb,0,0,0]	->	[.x.];
[.c.,0,0,^hb,0,0,0]	->	[.x.];
[.c.,0,1,^hb,8,0,0]	->	[.x.];
[.c.,0,0,^hb,8,0,0]	->	[.x.];
[.c.,0,0,^hb,8,0,0]	->	[.x.];
[.c.,0,0,^hb,8,0,0]	->	[.x.];
[.c.,0,0,^hb,8,0,0]	->	[.x.];
[.c.,0,0,^hb,8,0,0]	->	[.x.];
[.c.,0,0,^hb,8,0,0]	->	[.x.];
[.c.,0,0,^hb,8,0,0]	->	[.x.];
[.c.,0,0,^hb,8,0,0]	->	[.x.];

END