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📄 2zhamen.asm

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💻 ASM
字号:
	;Cspa223.asm

EPROM   EQU     2000H
FPGA	EQU     8000H
CTC	EQU	0A000H

AX	EQU	1CH
BX	EQU	1EH
CX	EQU	20H
DX	EQU	22H
PX	EQU	24H
QX	EQU	26H
IX	EQU	28H
HX	EQU	2AH
YX      EQU     2CH
ZX      EQU     2EH

AL	EQU	1CH
AH	EQU	1DH
BL	EQU	1EH
BH	EQU	1FH
CL	EQU	20H
CH	EQU	21H
DL	EQU	22H
DH	EQU	23H
PL	EQU	24H
PH	EQU	25H
QL	EQU	26H
QH	EQU	27H
IL	EQU	28H
IH	EQU	29H

ZL	EQU	2EH
ZH	EQU	2FH

CSPCNT	 	EQU	30H
INITS		EQU	32H
SYNCS		EQU	33H
FLAGB		EQU	34H
FPGAS		EQU	35H

CH0		EQU	36H
CH1		EQU	38H
ADCH		EQU	3AH
AMODE           EQU     3CH
PACNT		EQU	3EH

AMPD		EQU	40H
AMPS		EQU	42H
AMODE1          EQU     44H

CAPCOMP0_CON_W	EQU	0E0H	;WSR=7AH 1F40H
CAPCOMP0_TIME_W	EQU	0E2H	;WSR=7AH 1F42H
CAPCOMP1_CON_W	EQU	0E4H	;WSR=7AH 1F44H
CAPCOMP1_TIME_W	EQU	0E6H	;WSR=7AH 1F46H
CAPCOMP2_CON_W	EQU	0E8H	;WSR=7AH 1F48H
CAPCOMP2_TIME_W	EQU	0EAH	;WSR=7AH 1F4AH
CAPCOMP3_CON_W	EQU	0ECH	;WSR=7AH 1F4CH
CAPCOMP3_TIME_W	EQU	0EEH	;WSR=7AH 1F4EH

COMP0_CON_W	EQU	0F8H	;WSR=7AH 1F58H
COMP0_TIME_W	EQU	0FAH	;WSR=7AH 1F5AH
COMP1_CON_W	EQU	0FCH	;WSR=7AH 1F5CH
COMP1_TIME_W	EQU	0FEH	;WSR=7AH 1F5EH

COMP2_CON_W	EQU	0E0H	;WSR=7BH 1F60H
COMP2_TIME_W	EQU	0E2H	;WSR=7BH 1F62H
COMP3_CON_W	EQU	0E4H	;WSR=7BH 1F64H
COMP3_TIME_W	EQU	0E6H	;WSR=7BH 1F66H

COMP3_CON	EQU	1F64H
COMP3_TIME	EQU	1F66H

T1CONTROL_W	EQU	0F8H	;WSR=7BH 1F78H
TIMER1_W	EQU	0FAH	;WSR=7BH 1F7AH
T2CONTROL_W	EQU	0FCH	;WSR=7BH 1F7CH
TIMER2_W	EQU	0FEH	;WSR=7BH 1F7EH

P0_PIN_W	EQU	0E8H	;WSR=7DH 1FA8H
P1_PIN_W	EQU	0E9H	;WSR=7DH 1FA9H
AD_RESULT_W	EQU	0EAH	;WSR=7DH 1FAAH
AD_COMMAND_W	EQU	0ECH	;WSR=7DH 1FACH
AD_TEST_W	EQU	0EEH	;WSR=7DH 1FAEH
AD_TIME_W	EQU	0EFH	;WSR=7DH 1FAFH

PWM0_W		EQU	0F0H	;WSR=7DH 1FB0H
PWM1_W		EQU	0F2H	;WSR=7DH 1FB2H
PWM_PERIOD_W	EQU	0F4H	;WSR=7DH 1FB4H
PWM1_PER_CNT_W	EQU	0F2H	;WSR=7DH 1FB2H

PI_MASK_W	EQU	0FCH	;WSR=7DH 1FBCH
PI_PEND_W	EQU	0FEH	;WSR=7DH 1FBEH

WG_OUT_W	EQU	0E0H 	;WSR=7EH 1FC0H
WG_COMP1_W	EQU	0E2H 	;WSR=7EH 1FC2H
WG_COMP2_W	EQU	0E4H 	;WSR=7EH 1FC4H
WG_COMP3_W	EQU	0E6H 	;WSR=7EH 1FC6H
WG_RELOAD_W	EQU	0E8H	;WSR=7EH 1FC8H
WG_COUNT_W	EQU	0EAH 	;WSR=7EH 1FCAH
WG_CON_W	EQU	0ECH 	;WSR=7EH 1FCCH
WG_PROTECT_W	EQU	0EEH 	;WSR=7EH 1FCEH

P2_MODE_W	EQU	0F0H 	;WSR=7EH 1FD0H
P2_DIR_W	EQU	0F2H 	;WSR=7EH 1FD2H
P2_REG_W	EQU	0F4H 	;WSR=7EH 1FD4H
P2_PIN_W	EQU	0F6H 	;WSR=7EH 1FD6H

P2_MODE		EQU	1FD0H
P2_DIR		EQU	1FD2H
P2_REG		EQU	1FD4H
P2_PIN		EQU	1FD6H

P5_REG		EQU	1FF5H
P5_DIR		EQU	1FF3H
P5_MODE		EQU	1FF1H

R0		EQU	00H
PTSSEL		EQU	04H
PTSSEL1		EQU	05H
PTSSRV		EQU	06H
PTSSRV1		EQU	07H
INT_MASK	EQU	08H
INT_PEND	EQU	09H
WDOG		EQU	0AH
INT_PEND1	EQU	12H
INT_MASK1	EQU	13H
WSR		EQU	14H
SP		EQU	18H


        ORG 2000H
  DCW 2080H,2080H,CAP0INT,2080H,CAP1INT
  DCW 2080H,CAP2INT,COMP2INT,2080H,2080H

	ORG	2014H
	DCW	8008H

	ORG	2018H
RCCR:	DCW	200CH,20DEH,20FFH,20FFH
	ORG	2020H
	DCW	200CH,20DEH,20FFH,20FFH

	ORG 2030H
  DCW CAP3INT,2080H,2080H,2080H,2080H,2080H
  DCW EXINT,2080H

	ORG	2050H
	DCW	0050H

	ORG	2080H
	LD	SP,#0DEH
	DI
	DPTS
	CMPB	INITS,#55H
	JE	WGT
	LCALL	DAINIT

WGT:	CLRB	SYNCS
	CLRB	FLAGB
	CLR	CSPCNT
        LD      DX,R0
        CLR     AMPS
	LDBZE	PACNT,FPGA+5
	LDB	IL,FPGA+6
	LDB	IH,FPGA+7

	LDB	WSR,#7EH
	LDB	P2_MODE_W,#01100000B
	LDB	P2_REG_W,#11011111B
	LDB	P2_DIR_W,#00001111B

	LDB	AL,#10001111B
	STB	AL,P5_REG[0]
	LDB	AL,#10000000B
	STB	AL,P5_DIR[0]
	LDB	AL,#00001111B
	STB	AL,P5_MODE[0]

	LDB	WSR,#7BH
	LD	T1CONTROL_W,#11000000B
	LD	T2CONTROL_W,#11000000B

	;WGINIT
	LDB	WSR,#7EH
	LD	WG_OUT_W,#0E73FH
	LDB	WG_PROTECT_W,#00001111B
	LD	WG_COMP1_W,#400		;50wS
	LD	WG_COMP2_W,#480		;60wS
	LD	WG_COMP3_W,#560		;70wS
	LD	WG_RELOAD_W,#3208
        LD      WG_CON_W,#2C06H

	;CAPCOMINIT
	LDB	WSR,#7AH
	LDB	CAPCOMP0_CON_W,#00100111B	;Bt up
	LD	R0,CAPCOMP0_TIME_W
	LDB	CAPCOMP1_CON_W,#10010001B	;Bt down
	LD	R0,CAPCOMP1_TIME_W
	LDB	CAPCOMP2_CON_W,#00010000B	;0_sync up
	LD	R0,CAPCOMP2_TIME_W
	LDB	CAPCOMP3_CON_W,#00100011B	;Fm up
	LD	R0,CAPCOMP3_TIME_W

	LDB	COMP1_CON_W,#11101000B		;UP_H
	LD	COMP1_TIME_W,#720		;180wS

	LDB	WSR,#7BH
	LDB	COMP2_CON_W,#11011000B		;down
	LD	COMP2_TIME_W,#760		;190wS


	LDB	WSR,#7DH
	LDB	AD_TIME_W,#67H			;1wS_4wS
	LDB	AD_TEST_W,#08H

	;8254INIT
	LDB	AMODE,#00110000B	;MODE0 ;读FT
	STB	AMODE,CTC+3
	STB	R0,CTC
	STB	R0,CTC

	LDB	AL,#01110110B	;MODE3
	STB	AL,CTC+3
	LD	AX,#2000		;250wS 4KZ
	STB	AL,CTC+1
 	STB	AH,CTC+1

 	LDB	AL,#10110110B	;MODE3
	STB	AL,CTC+3
	LD	AX,#2400		;300wS 3.3K
        STB	AL,CTC+2
	STB	AH,CTC+2

       ; LDB	AMODE1,#10110000B	;MODE0 读BT
	;STB	AMODE1,CTC+3
	;STB	R0,CTC+2
	;STB	R0,CTC+2

	LDB	WSR,#7EH
        LD      WG_CON_W,#3C06H

	LDB	WSR,#7DH
	LDB	PI_MASK_W,#00000000B
	CLRB	PI_PEND_W

	LD	R0,1F42H	;CAPCOMP0_TIME
	LD	R0,1F46H	;CAPCOMP1_TIME
	LD	R0,1F4AH	;CAPCOMP2_TIME
	LD	R0,1F4EH	;CAPCOMP3_TIME
	CLRB	FPGAS

	CLRB	INT_PEND
	CLRB	INT_PEND1

	LDB	INT_MASK,#11010100B
	LDB	INT_MASK1,#01000001B
	EI

	SJMP	BEGAN

		ORG	2200H
BEGAN:		CMPB	SYNCS,#55H
		JNE	BE1

		CMPB	FLAGB,#0AAH
		JNE	BE0
		LCALL   CALCUL
		SJMP	BE1

BE0:	        nop
        	LD	AX,1F7EH[0]	;T2
		CMP	AX,#360		;B-90wS
		JNH	BE1
		LD	DX,CSPCNT
		SHL	DX,#1

		LCALL	OUT

BE1:		JBC	FPGAS,0,BE2
		LCALL	MDA
BE2:		EI
        	LDB	INT_MASK,#11010100B
	        LDB	INT_MASK1,#01000001B
;		LDB	WDOG,#1EH
;		LDB	WDOG,#0E1H
		SJMP	BEGAN

		ORG	2300H
CAP2INT:	DI
		LD	R0,1F4AH[0]	;READ CAPCOMP2_TIME
        	LD	CSPCNT,R0
;              	JBC	AMPS,0,CAP22
;		STB	AMPD+1,FPGA+0
;		STB	AMPD,FPGA+1
;		CLRB	AMPS
CAP22:          EI
		RET

		ORG	2350H
CAP0INT:	DI
		LD	R0,1F42H	;CAPCOMP0_TIME
		LDB	FLAGB,#55H
		EI
		RET

		ORG	23A0H
CAP1INT:	PUSHA
		CMPB	FLAGB,#55H
		JNE	CAP10
		LD	PX,1F46H[0]	;READ CAPCOMP1_TIME
		SHL	PX,#1		;1/8wS
                LD      ZX,PX
		LDB	FLAGB,#0AAH
		POPA
		RET

CAP10:		LD	R0,1F46H
		CLRB	FLAGB
		POPA
		RET


		ORG	2400H
CAP3INT:	PUSHA
		LD	R0,1F4EH
		INC	CSPCNT
		AND	CSPCNT,#0003H   ;#0007H	;G=0--7
		JBS    	CSPCNT,0,CAP31    ;双数通道不发送衰减,报警等值
		JBC	AMPS,0,CAP31
		STB	AMPD+1,FPGA+0     ;单数通道向主机接收板发送衰减,报警电平
		STB	AMPD,FPGA+1
		CLRB	AMPS
CAP31:  	
		LDB	AMODE,#00110000B	;MODE0 ;读FT
        	STB	AMODE,CTC+3
        	STB	R0,CTC
	        STB	R0,CTC

               ; LDB	AMODE1,#10110000B	;MODE0 读BT
	       ; STB	AMODE1,CTC+3
        	;STB	R0,CTC+2
	        ;STB	R0,CTC+2

		LDB	SYNCS,#55H
		CLRB	FLAGB
		POPA
		RET

		ORG	24A0H
COMP2INT:	PUSHA
		LDB	WSR,#7EH
		LDB	P2_MODE_W,#01000000B
		ANDB	P2_REG_W,#11011111B
		LDB	P2_MODE_W,#01100000B
		POPA
		RET

		ORG	2600H
CALCUL:		LD	DX,CSPCNT
		SHL	DX,#1
                LD	AX,0130H[0]
		CMP	AX,#0055H
		JNE	CA1

NOCHGO:		LD	AX,0110H[DX]
		ST	ZX,01B0H[DX]
		SJMP	OUT

CA1:		LD	AX,0110H[DX]
		SUB	AX,0134H	;SET-3wS
		CMP	PX,AX
		JNH	OUT

		LD	AX,0110H[DX]
		ADD	AX,0136H	;SET+3wS
		CMP	PX,AX
		JH	OUT

CA3:		SUB	PX,01B0H[DX]
		JGE	CA4
		NEG	PX
		CMP	PX,#16		;2wS
		JH	OUT
		CMP	PX,#12		;1.5wS
		JH	CA33
		CMP	PX,#8		;1wS
		JH	CA32
		CMP	PX,#4		;0.5wS
		JH	CA31
                SHL	PX,#2
CA31:           SHL     PX,#2
CA32:		SHL	PX,#1
CA33:           NEG     PX
		SJMP	CA43

CA4:		CMP	PX,#16		;2wS
		JH	OUT
		CMP	PX,#12		;1.5wS
		JH	CA43
		CMP	PX,#8		;1wS
		JH	CA42
		CMP	PX,#4		;0.5wS
		JH	CA41
                SHL	PX,#2
CA41:           SHL     PX,#2
CA42:		SHL	PX,#1
CA43:           ADD     PX,01A0H[DX]
                LDBSE   AX,PH
		CLRB	PH
		ST	PX,01A0H[DX]
		ADD	AX,01B0H[DX]
		ST	AX,01B0H[DX]

OUT:		LDB	ADCH,#00110000B
		STB	ADCH,1FACH		;AD COMMAND Fv

        	LD	AX,0110H[DX] ;  NOT TRACE
		ST	ZX,01B0H[DX] ;

		LDB	QL,CTC      ;读FT
		LDB	QH,CTC
                NOT     QX
		CMP	DX,R0       ;如果是0通道时,高位置1
		JNE	OUT1
		OR      QX,#8000H
OUT1:		STB	QL,FPGA+2
		STB	QH,FPGA+3
		LD	AX,01B0H[DX]
		STB	AL,FPGA+4
		STB	AH,FPGA+5

;		LDB	QL,CTC+2     ;读BT
;		LDB	QH,CTC+2
;                NOT     QX
;	        STB	QL,FPGA+4
;		STB	QH,FPGA+5

                INC	DX
		INC	DX
		AND	DX,#0007H       ;#000FH

		LD	CH0,1FAAH
		LDB	ADCH,#00110001B
		STB	ADCH,1FACH	;AD COMMAND
		STB	CH0+1,FPGA+6		;Fv

CALCUL1:	LD	AX,01B0H[DX]
		SUB	BX,AX,0132H
                SUB     BX,0138H
		ST	BX,1FC4H[0]	;WG_COMP2 F_CLOS B_OPEN
		SUB	CX,BX,0100H[DX]
		JNH	CALCUL3
		SUB	CX,0132H
		JNH	CALCUL3
		CMP	CX,#8
		JH	CALCUL4
CALCUL3:	LD	CX,#8
CALCUL4:	ST	CX,1FC2H[0]	;WG_COMP1 F_OPEN
		ADD	BX,0120H[DX]
		ST	BX,1FC6H[0]	;WG_COMP3 B_CLOS
		CLRB	SYNCS
		CLRB	FLAGB
		LD	CH1,1FAAH
		STB	CH1+1,FPGA+7		;Bv
		RET

		ORG	2800H
EXINT:		DI
		LDBZE	PACNT,FPGA+5
		LDB	IH,FPGA+6
		LDB	IL,FPGA+7
		ST	IX,0100H[PACNT]
		LDB	FPGAS,#01H
;                STB	AH,FPGA+2     ;SHIYAN.C 中的试验程序
;		STB	AL,FPGA+3
;		STB	BH,FPGA+4
;		STB	BL,FPGA+5
;               STB	CH,FPGA+6
;		STB	CL,FPGA+7
                EI
		RET

		ORG	2880H
MDA:		LD	HX,PACNT
                CMP     HX,#0FH
                JNH     MDA4

                CMP     HX,#1FH
                JH      MDA0
                LD      YX,0100H[HX]
                ST      YX,01A0H[HX]	;01B0H
                SJMP    MDA4

MDA0:		CMP	HX,#2FH
		JNH	MDA4
		CMP	HX,#3FH
		JNH	MDA1

		LD	AMPD,0100H[HX]      ;HX大于3F时是衰减参数、报警参数抑制参数。
		LDB	AMPS,#01H           ;接收到衰减或报警抑制变化的标志。
		SJMP	MDA4

MDA1:		CMP	HX,#32H
		JNE	MDA2
		LD	BX,0132H[0]
		AND	BX,#001FH
		LD	AX,#3C00H
		OR	AX,BX
		ST	AX,1FCCH[0]
		SJMP	MDA4

MDA2:		CMP	HX,#3AH
		JNE	MDA4
		LD	AX,013AH		;250wS 4KZ
		LDB	BL,#01110110B		;MODE3
		STB	BL,0A003H[0]
		STB	AL,0A001H[0]
 		STB	AH,0A001H[0]

MDA4:		CLRB	FPGAS
		RET


	ORG	2A00H
DAINIT: CLR     DX
        LDB     CL,#56
DAINIT1:LD	AX,DBTAB[DX]
	ST	AX,0100H[DX]
	INC     DX
	INC	DX
	DJNZ	CL,DAINIT1

	CLR	DX
	LDB	CL,#8
DAINIT2:ST	R0,01A0H[DX]
	LD	AX,0110H[DX]
	ST	AX,01B0H[DX]
	INC	DX
	INC	DX
	DJNZ	CL,DAINIT2
	LDB	INITS,#55H
	RET

	ORG	3000H
DBTAB:	DB 10H,00H,10H,00H,10H,00H,10H,00H,10H,00H,10H,00H,10H,00H,10H,00H;2wS
  	DB 60H,00H,60H,00H,60H,00H,60H,00H,60H,00H,60H,00H,60H,00H,60H,00H;11w
	DB 40H,00H,40H,00H,40H,00H,40H,00H,40H,00H,40H,00H,40H,00H,40H,00H;8wS
        DB 00H,00H,06H,00H,14H,00H,14H,00H,0AH,00H,0D0H,07H,10H,00H,80H,00H
        ;  #18H     0.75wS  2.5wS   2.5wS   1.25wS   250wS   PWM0    PWM1
        DB 00H,20H,01H,20H,02H,20H,03H,20H,04H,20H,05H,20H,06H,20H,07H,20H
        DB 08H,20H,09H,20H,0AH,20H,0BH,20H,0CH,20H,0DH,20H,0EH,20H,0FH,20H
        DB 10H,20H,11H,20H,12H,20H,13H,20H,14H,20H,15H,20H,16H,20H,17H,20H
	END

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