📄 csp_gpt.h
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/*-----------------------------------------------------------------------------
* EUROPE TECHNOLOGIES Software Support
*------------------------------------------------------------------------------
* The software is delivered "AS IS" without warranty or condition of any
* kind, either express, implied or statutory. This includes without
* limitation any warranty or condition with respect to merchantability or
* fitness for any particular purpose, or against the infringements of
* intellectual property rights of others.
*------------------------------------------------------------------------------
*
* File Name : csp_gpt.h
* Description : Definitions, Macros and function declarations for
* General Purpose Timer module
* Library Version : 2.00
* Module Version : 1.XX
*
* +----- (NEW | MODify | ADD | DELete)
* |
* No | When Who What
*-----+---+----------+------------------+--------------------------------------
* 000 NEW 01/05/99 Patrice VILCHEZ Creation
* 001 MOD 01/04/01 Olivier MAZUYER Clean up
* 002 MOD 08/06/01 Frederic SAMSON Clean Up
* 003 MOD 25/10/01 Christophe GARDIN Clean Up
*----------------------------------------------------------------------------*/
#ifndef CSP_GPT_H
#define CSP_GPT_H
/******************************************************************************
************************** GPT Structure Definition ***************************
******************************************************************************/
/* Physical Timer Definition */
#define GPT_ONE_CHANNEL 1u
#define GPT_THREE_CHANNEL 3u
/******************************************************************************
* GPT Channel Structure
******************************************************************************/
typedef struct
{
CSP_REGISTER_T PER; /* PIO Enable Register */
CSP_REGISTER_T PDR; /* PIO Disable Register */
CSP_REGISTER_T PSR; /* PIO Status Register */
CSP_REGISTER_T ReservedA;
CSP_REGISTER_T OER; /* Output Enable Register */
CSP_REGISTER_T ODR; /* Output Disable Register */
CSP_REGISTER_T OSR; /* Output Status Register */
CSP_REGISTER_T ReservedB[5];
CSP_REGISTER_T SODR; /* Set Output Data Register */
CSP_REGISTER_T CODR; /* Clear Output Data Register */
CSP_REGISTER_T ODSR; /* Output Data Status Register */
CSP_REGISTER_T PDSR; /* Pin Data Status Register */
CSP_REGISTER_T MDER; /* Multi-Driver Enable Register */
CSP_REGISTER_T MDDR; /* Multi-Driver Disable Register */
CSP_REGISTER_T MDSR; /* Multi-Driver Status Register */
CSP_REGISTER_T ReservedC;
CSP_REGISTER_T ECR; /* Enable Clock Register */
CSP_REGISTER_T DCR; /* Disable Clock Register */
CSP_REGISTER_T PMSR; /* Power Management Status Register */
CSP_REGISTER_T ReservedD;
CSP_REGISTER_T CR; /* Control Register */
CSP_REGISTER_T MR; /* Mode Register */
CSP_REGISTER_T ReservedE[2];
CSP_REGISTER_T SR; /* Status Register */
CSP_REGISTER_T IER; /* Interrupt Enable Register */
CSP_REGISTER_T IDR; /* Interrupt Disable Register */
CSP_REGISTER_T IMR; /* Interrupt Mask Register */
CSP_REGISTER_T CV; /* Counter value Register */
CSP_REGISTER_T RA; /* Register A */
CSP_REGISTER_T RB; /* Register B */
CSP_REGISTER_T RC; /* Register C */
CSP_REGISTER_T ReservedF[28];
} CSP_GPT_T, *CSP_GPT_PTR;
/******************************************************************************
* GPT 1 Channel Structure
******************************************************************************/
typedef struct
{
CSP_GPT_T CHANNEL[GPT_ONE_CHANNEL]; /* GPT Channel */
CSP_REGISTER_T ReservedA[192];
CSP_REGISTER_T TSTC; /* Test Control Register */
CSP_REGISTER_T TSTM; /* Test Mode Register */
} CSP_GPT1C_T, *CSP_GPT1C_PTR;
/******************************************************************************
* GPT 3 Channels Structure
******************************************************************************/
typedef struct
{
CSP_GPT_T CHANNEL[GPT_THREE_CHANNEL]; /* GPT Channel */
CSP_REGISTER_T BCR; /* Block Control Register */
CSP_REGISTER_T BMR; /* Clock Mode Register */
CSP_REGISTER_T ReservedA[62];
CSP_REGISTER_T TSTC; /* Test Control Register */
CSP_REGISTER_T TSTM; /* Test Mode Register */
} CSP_GPT3C_T, *CSP_GPT3C_PTR;
/******************************************************************************
************************** GPT Registers Definition ***************************
******************************************************************************/
/******************************************************************************
* PER, PDR, PSR, OER, ODR, OSR, :
* SODR, CODR, ODSR, PDSR, MDER, MDDR : GPT PIO Registers, Status Register and
* MDSR, SR, IER, IDR, IMR : Interrupt Registers
******************************************************************************/
#define TIOB (0x01ul << 16) /* TIOB */
#define TIOA (0x01ul << 17) /* TIOA */
#define TCLK (0x01ul << 18) /* TCLK */
/******************************************************************************
* ECR, DCR, PMSR : GPT Power Management Registers
******************************************************************************/
#define PIO (0x01ul << 0) /* PIO Clock */
#define TC (0x01ul << 1) /* GPT Clock */
/******************************************************************************
* CR : GPT Control Register
******************************************************************************/
#define SWRST (0x01ul << 0) /* GPT Software Reset */
#define CLKEN (0x01ul << 1) /* Counter Clock Enable */
#define CLKDIS (0x01ul << 2) /* Counter Clock Disable */
#define SWTRG (0x01ul << 3) /* Software Trigger */
/******************************************************************************
* MR : GPT Mode Register (Capture mode)
******************************************************************************/
/* CLKS : Clock Source */
#define CLKS (0x07ul << 0) /* CLKS Mask */
#define CLKS_MCK2 (0x00ul << 0) /* MCK/2 */
#define CLKS_MCK8 (0x01ul << 0) /* MCK/8 */
#define CLKS_MCK32 (0x02ul << 0) /* MCK/32 */
#define CLKS_MCK128 (0x03ul << 0) /* MCK/128 */
#define CLKS_MCK1024 (0x04ul << 0) /* MCK/1024 */
#define CLKS_XC0 (0x05ul << 0) /* External XC0 */
#define CLKS_XC1 (0x06ul << 0) /* External XC1 */
#define CLKS_XC2 (0x07ul << 0) /* External XC2 */
/* CLKI : Clock Inverter */
#define CLKINV (0x01ul << 3)
/* BURST : Burst Signal */
#define BURST (0x03ul << 4) /* BURST Mask */
#define BURST_NONE (0x00ul << 4) /* No signal selected for burst */
#define BURST_XC0 (0x01ul << 4) /* XC0 selected for burst */
#define BURST_XC1 (0x02ul << 4) /* XC1 selected for burst */
#define BURST_XC2 (0x03ul << 4) /* XC2 selected for burst */
/* LDBSTOP : Counter clock stopped with RB Loading */
#define LDBSTOP (0x01ul << 6)
/* LDBDIS : Counter clock disable with RB Loading */
#define LDBDIS (0x01ul << 7)
/* ETRGEDG : External Trigger Edge */
#define ETRGEDG (0x03ul << 8) /* ETRGEDG Mask */
#define ETRGEDG_NONE (0x00ul << 8) /* No external trigger */
#define ETRGEDG_RISING (0x01ul << 8) /* Rising edge trigger */
#define ETRGEDG_FALLING (0x02ul << 8) /* Falling edge trigger */
#define ETRGEDG_EACH (0x03ul << 8) /* Each edge trigger */
/* ABETRG : TIOA or TIOB External Trigger */
#define ABETRG (0x01ul << 10) /* ABETRG Mask */
#define ABETRG_TIOA (0x01ul << 10) /* TIOA selected for external trigger */
#define ABETRG_TIOB (0x00ul << 10) /* TIOB selected for external trigger */
/* CPCTRG : RC Compare Trigger Enable */
#define CPCTRG (0x01ul << 14)
/* WAVE = CAPT_ENA : Capture Mode is enabled */
#define WAVE (0x01ul << 15) /* WAVE Mask */
#define CAPT_ENA (0x00ul << 15) /* Capture Mode */
#define WAVE_ENA (0x01ul << 15) /* Waveform Mode */
/* LDRA : Load RA */
#define LDRA (0x03ul << 16) /* LDRA Mask */
#define LDRA_NONE (0x00ul << 16) /* No external trigger selected */
#define LDRA_RISING (0x01ul << 16) /* Rising edge on TIOA */
#define LDRA_FALLING (0x02ul << 16) /* Falling edge on TIOA */
#define LDRA_EACH (0x03ul << 16) /* Each edge on TIOA */
/* LDRB : Load RB */
#define LDRB (0x03ul << 18) /* LRRB Mask */
#define LDRB_NONE (0x00ul << 18) /* No external trigger selected */
#define LDRB_RISING (0x01ul << 18) /* Rising edge on TIOA */
#define LDRB_FALLING (0x02ul << 18) /* Falling edge on TIOA */
#define LDRB_EACH (0x03ul << 18) /* Each edge on TIOA */
/******************************************************************************
* MR : Mode Register (Waveform mode)
******************************************************************************/
/* CLKS : Clock source - Same as Capture Mode */
/* CLKI : Clock inverter - Same as Capture Mode */
/* BURST : Burst signal - Same as Capture Mode */
/* CPCSTOP : Compare RC Stops the counter */
#define CPCSTOP (0x01ul << 6) /* CPCSTOP Mask */
#define CPCSTOP_DIS (0x00ul << 6) /* Counter is not stopped when equal condition on RC */
#define CPCSTOP_ENA (0x01ul << 6) /* Counter is stopped when equal condition on RC */
/* CPCDIS : Compare RC Disables Clock */
#define CPCSDIS (0x01ul << 7) /* CPCSDIS Mask */
#define CPCSDIS_DIS (0x00ul << 7) /* Counter clock is disables when equal condition on RC */
#define CPCSDIS_ENA (0x01ul << 7) /* Counter clock disables when equal condition on RC */
/* EEVTEDG : External Event Edge */
#define EEVTEDG (0x03ul << 8) /* EEVTEDG Mask */
#define EEVTEDG_NONE (0x00ul << 8) /* No external event edge */
#define EEVTEDG_RISING (0x01ul << 8) /* Rising event edge */
#define EEVTEDG_FALLING (0x02ul << 8) /* Falling event edge */
#define EEVTEDG_EACH (0x03ul << 8) /* Each event edge */
/* EEVT : External Event */
#define EEVT (0x03ul << 10) /* EEVT Mask */
#define EEVT_TIOB (0x00ul << 10) /* TIOB External Trigger */
#define EEVT_XC0 (0x01ul << 10) /* XC0 External Trigger */
#define EEVT_XC1 (0x02ul << 10) /* XC1 External Trigger */
#define EEVT_XC2 (0x03ul << 10) /* XC2 External Trigger */
/* ENETRG : Enable External Trigger */
#define ENETRG (0x01ul << 12)
/* CPCTRG : RC compare trigger enable - Same as Capture Mode */
/* WAVE = WAVE_ENA : Waveform mode is enable */
/* ACPA : RA Compare Effect on TIOA */
#define ACPA (0x03ul << 16) /* ACPA Mask */
#define ACPA_NONE (0x00ul << 16) /* No effect on TIOA output */
#define ACPA_SET (0x01ul << 16) /* SET TIOA output */
#define ACPA_CLEAR (0x02ul << 16) /* Clear TIOA output */
#define ACPA_TOGGLE (0x03ul << 16) /* Toggle TIOA output */
/* ACPC : RC Compare Effect on TIOA */
#define ACPC (0x03ul << 18) /* ACPC Mask */
#define ACPC_NONE (0x00ul << 18) /* No effect on TIOA output */
#define ACPC_SET (0x01ul << 18) /* SET TIOA output */
#define ACPC_CLEAR (0x02ul << 18) /* Clear TIOA output */
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