📄 csp_usart.h
字号:
/*-----------------------------------------------------------------------------
* EUROPE TECHNOLOGIES Software Support
*------------------------------------------------------------------------------
* The software is delivered "AS IS" without warranty or condition of any
* kind, either express, implied or statutory. This includes without
* limitation any warranty or condition with respect to merchantability or
* fitness for any particular purpose, or against the infringements of
* intellectual property rights of others.
*------------------------------------------------------------------------------
*
* File Name : csp_usart.h
* Description : Definitions, Macros and function declarations for
* Universal Synchronous/Asynchronous Receiver/Transmitter module
* Library Version : 2.00
* Module Version : 1.XX
*
* +----- (NEW | MODify | ADD | DELete)
* |
* No | When Who What
*-----+---+----------+------------------+--------------------------------------
* 000 NEW 01/05/99 Patrice VILCHEZ Creation
* 001 MOD 01/04/01 Olivier MAZUYER Clean up
* 002 MOD 08/06/01 Frederic SAMSON Clean Up
* 003 MOD 22/10/01 Christophe GARDIN Clean Up
* 004 MOD 18/07/02 Christophe GARDIN Add LIN Registers
*----------------------------------------------------------------------------*/
#ifndef CSP_USART_H
#define CSP_USART_H
/******************************************************************************
************************ USART Structure Definition ***************************
******************************************************************************/
typedef struct
{
CSP_REGISTER_T PER; /* PIO Enable Register */
CSP_REGISTER_T PDR; /* PIO Disable Register */
CSP_REGISTER_T PSR; /* PIO Status Register */
CSP_REGISTER_T ReservedA;
CSP_REGISTER_T OER; /* Output Enable Register */
CSP_REGISTER_T ODR; /* Output Disable Register */
CSP_REGISTER_T OSR; /* Output Status Register */
CSP_REGISTER_T ReservedB[5];
CSP_REGISTER_T SODR; /* Set Output Data Register */
CSP_REGISTER_T CODR; /* Clear Output Data Register */
CSP_REGISTER_T ODSR; /* Output Data Status Register */
CSP_REGISTER_T PDSR; /* Pin Data Status Register */
CSP_REGISTER_T MDER; /* Multi-Driver Enable Register */
CSP_REGISTER_T MDDR; /* Multi-Driver Disable Register */
CSP_REGISTER_T MDSR; /* Multi-Driver Status Register */
CSP_REGISTER_T ReservedC;
CSP_REGISTER_T ECR; /* Enable Clock Register */
CSP_REGISTER_T DCR; /* Disable Clock Register */
CSP_REGISTER_T PMSR; /* Power Management Status Register*/
CSP_REGISTER_T ReservedD;
CSP_REGISTER_T CR; /* Control Register */
CSP_REGISTER_T MR; /* Mode Register */
CSP_REGISTER_T ReservedE;
CSP_REGISTER_T CSR; /* Clear Status Register */
CSP_REGISTER_T SR; /* Status Register */
CSP_REGISTER_T IER; /* Interrupt Enable Register */
CSP_REGISTER_T IDR; /* Interrupt Disable Register */
CSP_REGISTER_T IMR; /* Interrupt Mask Register */
CSP_REGISTER_T RHR; /* Receiver Holding Register */
CSP_REGISTER_T THR; /* Transmit Holding Register */
CSP_REGISTER_T BRGR; /* Baud Rate Generator Register */
CSP_REGISTER_T RTOR; /* Receiver Time-out Register */
CSP_REGISTER_T TTGR; /* Transmitter Time-guard Register */
CSP_REGISTER_T LIR; /* LIN Identifier Register */
CSP_REGISTER_T DFWR0; /* Data Field Write 0 Register */
CSP_REGISTER_T DFWR1; /* Data Field Write 1 Register */
CSP_REGISTER_T DFRR0; /* Data Field Read 0 Register */
CSP_REGISTER_T DFRR1; /* Data Field Read 1 Register */
CSP_REGISTER_T SBLR; /* Sync Break Length Register */
} CSP_USART_T, *CSP_USART_PTR;
/******************************************************************************
************************* USART Registers Definition **************************
******************************************************************************/
/******************************************************************************
* PER, PDR, PSR, OER, ODR, OSR, :
* SODR, CODR, ODSR, PDSR, MDER, MDDR : USART PIO Registers, Status Registers and
* MDSR, SR, IER, IDR, IMR : Interrupt Registers
******************************************************************************/
#define SCK (0x01ul << 16) /* SCK */
#define TXD (0x01ul << 17) /* TXD */
#define RXD (0x01ul << 18) /* RXD */
/******************************************************************************
* ECR, DCR, PMSR : USART Power Management Registers
******************************************************************************/
#define PIO (0x01ul << 0) /* PIO Clock */
#define USART (0x01ul << 1) /* USART Clock */
/******************************************************************************
* CR : USART Control Register
******************************************************************************/
#define SWRST (0x01ul << 0) /* Software Reset */
#define RSTRX (0x01ul << 2) /* Reset Receiver */
#define RSTTX (0x01ul << 3) /* Reset Transmitter */
#define RXEN (0x01ul << 4) /* Receiver Enable */
#define RXDIS (0x01ul << 5) /* Receiver Disable */
#define TXEN (0x01ul << 6) /* Transmitter Enable */
#define TXDIS (0x01ul << 7) /* Transmitter Disable */
#define RSTSTA (0x01ul << 8) /* Reset Status Bits */
#define STTBRK (0x01ul << 9) /* Start Break */
#define STPBRK (0x01ul << 10) /* Stop Break */
#define STTTO (0x01ul << 11) /* Start Time-out */
#define SENDA (0x01ul << 12) /* Send Address */
#define STHEADER (0x01ul << 16) /* Start Header */
#define STRESP (0x01ul << 17) /* Start Response */
/******************************************************************************
* MR : USART Mode Register
******************************************************************************/
#define LIN (0x01ul << 0) /* Local Interconnect Network mode */
/* SENDTIME : Send Time */
#define SENDTIME (0x03ul << 2) /* SENDTIME Mask */
#define SENDTIME_0 (0x00ul << 2) /* Number of Time = 0 */
#define SENDTIME_1 (0x01ul << 2) /* Number of Time = 1 */
#define SENDTIME_2 (0x02ul << 2) /* Number of Time = 2 */
#define SENDTIME_3 (0x03ul << 2) /* Number of Time = 3 */
/* USCLKS : Clock Selection */
#define USCLKS (0x03ul << 4) /* USCLKS Mask */
#define USCLKS_MCKI (0x00ul << 4) /* Core Clock (MCKI) */
#define USCLKS_MCKI_8 (0x01ul << 4) /* Core Clock / 8 (MCKI/8) */
#define USCLKS_SCK (0x02ul << 4) /* External Clock (SCK) */
/* CHRL : Character Length */
#define CHRL (0x03ul << 6) /* CHRL Mask */
#define CHRL_5 (0x00ul << 6) /* Five bits length */
#define CHRL_6 (0x01ul << 6) /* Six bits length */
#define CHRL_7 (0x02ul << 6) /* Seven bits length */
#define CHRL_8 (0x03ul << 6) /* Height bits length */
/* SYNC : Synchronous Mode Select */
#define SYNC (0x01ul << 8) /* Synchronous mode */
#define ASYNC (0x00ul << 8) /* Asynchronous mode */
/* PAR : Parity Type */
#define PAR (0x07ul << 9) /* PAR Mask */
#define PAR_EVEN (0x00ul << 9) /* Even parity */
#define PAR_ODD (0x01ul << 9) /* Odd parity */
#define PAR_SPACE (0x02ul << 9) /* Space parity (forced to 0) */
#define PAR_MARK (0x03ul << 9) /* Mark parity (forced to 1) */
#define PAR_NO (0x04ul << 9) /* No parity */
#define PAR_MULTIDROP (0x06ul << 9) /* Multi Drop parity */
/* NBSTOP : Number of Stop Bits */
#define NBSTOP (0x03ul << 12) /* NBSTOP Mask */
#define NBSTOP_1 (0x00ul << 12) /* 1 Stop bit */
#define NBSTOP_15 (0x01ul << 12) /* 1.5 Stop bit */
#define NBSTOP_2 (0x02ul << 12) /* 2 Stop bit */
/* CHMODE : Channel Mode */
#define CHMODE (0x03ul << 14) /* CHMODE Mask */
#define CHMODE_NORMAL (0x00ul << 14) /* Normal channel */
#define CHMODE_AUTO (0x01ul << 14) /* Automatic echo channel */
#define CHMODE_LOCAL (0x02ul << 14) /* Local loop back channel */
#define CHMODE_REMOTE (0x03ul << 14) /* Remote loop back channel */
#define SMCARDPT (0x01ul << 16) /* Smart Card Protocol valid / not valid */
/* MODE9 : 9-Bit Character Length */
#define MODE8 (0x00ul << 17) /* 8-Bits Mode */
#define MODE9 (0x01ul << 17) /* 9-Bits Mode */
/* CLKO : Clock Output Select */
#define CLKO (0x01ul << 18) /* Clock Output */
#define CLKI (0x00ul << 18) /* Clock Input */
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -