📄 csp_can.h
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/*-----------------------------------------------------------------------------
* EUROPE TECHNOLOGIES Software Support
*------------------------------------------------------------------------------
* The software is delivered "AS IS" without warranty or condition of any
* kind, either express, implied or statutory. This includes without
* limitation any warranty or condition with respect to merchantability or
* fitness for any particular purpose, or against the infringements of
* intellectual property rights of others.
*------------------------------------------------------------------------------
*
* File Name : csp_can.h
* Description : Definitions, Macros and function declarations for
* Controller Area Network module
* Library Version : 2.00
* Module Version : 1.XX
*
* +----- (NEW | MODify | ADD | DELete)
* |
* No | When Who What
*-----+---+----------+------------------+--------------------------------------
* 000 NEW 01/05/99 Patrice VILCHEZ Creation
* 001 ADD 28/07/00 Patrice VILCHEZ Add peripheral & bits declaration
* 002 MOD 01/04/01 Olivier MAZUYER Clean up
* 003 ADD 24/05/01 Tristan BONHOMME Add Spy bit
* 004 ADD 26/05/01 Patrice VILCHEZ Add CSP_CAN_GET_ID(ID) Macro
Add CSP_CAN_SET_ID(ID) Macro
* 005 MOD 08/06/01 Frederic SAMSON Clean Up
* 006 MOD 26/10/01 Christophe GARDIN Clean Up
* 007 MOD 11/03/02 Christophe GARDIN Add macros
* 008 MOD 24/06/02 Christophe GARDIN Modify BD and DATA bits
*----------------------------------------------------------------------------*/
#ifndef CSP_CAN_H
#define CSP_CAN_H
/******************************************************************************
************************** CAN Structure Definition ***************************
******************************************************************************/
/* Number of CAN Channels */
#define NB_CAN_CHANNEL 32u
/******************************************************************************
* CAN Channel Structure
******************************************************************************/
typedef struct
{
CSP_REGISTER_T ReservedA[5];
CSP_REGISTER_T DRA; /* Data Register A Channel X */
CSP_REGISTER_T DRB; /* Data Register B Channel X */
CSP_REGISTER_T MSK; /* Mask Register Channel X */
CSP_REGISTER_T IR; /* Identifier Register Channel X */
CSP_REGISTER_T CR; /* Control Register Channel X */
CSP_REGISTER_T STP; /* Stamp Register Channel X */
CSP_REGISTER_T CSR; /* Clear Status Register Channel X */
CSP_REGISTER_T SR; /* Status Register Channel X */
CSP_REGISTER_T IER; /* Interrupt Enable Register Channel X */
CSP_REGISTER_T IDR; /* Interrupt Disable Register Channel X */
CSP_REGISTER_T IMR; /* Interrupt Mask Register Channel X */
} CSP_CAN_CHANNEL_T;
/******************************************************************************
* CAN Structure 32 Channels
******************************************************************************/
typedef struct
{
CSP_REGISTER_T ReservedA[20];
CSP_REGISTER_T ECR; /* Enable Clock Register */
CSP_REGISTER_T DCR; /* Disable Clock Register */
CSP_REGISTER_T PMSR; /* Power Management Status Register */
CSP_REGISTER_T ReservedB;
CSP_REGISTER_T CR; /* Control Register */
CSP_REGISTER_T MR; /* Mode Register */
CSP_REGISTER_T ReservedC;
CSP_REGISTER_T CSR; /* Clear Status Register */
CSP_REGISTER_T SR; /* Status Register */
CSP_REGISTER_T IER; /* Interrupt Enable Register */
CSP_REGISTER_T IDR; /* Interrupt Disable Register */
CSP_REGISTER_T IMR; /* Interrupt Mask Register */
CSP_REGISTER_T CISR; /* Clear Interrupt Source Register */
CSP_REGISTER_T ISSR; /* Interrupt Source Status Register */
CSP_REGISTER_T SIER; /* Source Interrupt Enable Register */
CSP_REGISTER_T SIDR; /* Source Interrupt Disable Register */
CSP_REGISTER_T SIMR; /* Source Interrupt Mask Register */
CSP_REGISTER_T ReservedD[22];
CSP_CAN_CHANNEL_T CHANNEL[NB_CAN_CHANNEL]; /* CAN Channels */
} CSP_CAN_T, *CSP_CAN_PTR;
/******************************************************************************
************************** CAN Registers Definition ***************************
******************************************************************************/
/******************************************************************************
* ECR, DCR, PMSR : CAN Power Management Registers
******************************************************************************/
#define CAN (0x01ul << 1) /* CAN Clock */
/******************************************************************************
* CR : CAN Control Register
******************************************************************************/
#define SWRST (0x01ul << 0) /* CAN Software Reset */
#define CANEN (0x01ul << 1) /* CAN Enable */
#define CANDIS (0x01ul << 2) /* CAN Disable */
#define ABEN (0x01ul << 3) /* Abort Request Enable */
#define ABDIS (0x01ul << 4) /* Abort Request Disable */
#define OVEN (0x01ul << 5) /* Overload Request Enable */
#define OVDIS (0x01ul << 6) /* Overload Request Disable */
/******************************************************************************
* MR : CAN Mode Register
******************************************************************************/
/* BD : Baud rate Prescalar */
#define BD_MASK (0x3Ful << 0) /* Mask */
#define BD(val) (((val) & 0x3Ful) << 0) /* Writing Macro */
/* PROP : Propagation Segment Value */
#define PROP_MASK (0x07ul << 8) /* Mask */
#define PROP(val) (((val) & 0x07ul) << 8) /* Writing Macro */
/* SJW : Synchronization Jump width */
#define SJW_MASK (0x03ul << 12) /* Mask */
#define SJW(val) (((val) & 0x03ul) << 12) /* Writing Macro */
#define SMP (0x01ul << 14) /* Sampling Mode */
/* PHSEG1 : Phase Segment 1 Value */
#define PHSEG1_MASK (0x07ul << 16) /* Mask */
#define PHSEG1(val) (((val) & 0x07ul) << 16) /* Writing Macro */
/* PHSEG2 : Phase Segment 2 Value */
#define PHSEG2_MASK (0x07ul << 20) /* Mask */
#define PHSEG2(val) (((val) & 0x07ul) << 20) /* Writing Macro */
/******************************************************************************
* CSR, SR, IER, IDR, IMR : CAN Status and Interrupt Registers
******************************************************************************/
#define ENDINIT (0x01ul << 2) /* End of CAN Initialization */
/* SR, IER, IDR, IMR Registers Only */
#define ERPAS (0x01ul << 3) /* Error Passive */
#define BUSOFF (0x01ul << 4) /* Bus Off */
/* SR Register Only */
#define CANENA (0x01ul << 0) /* CAN Enable */
#define CANINIT (0x01ul << 1) /* CAN Initialized */
#define ABRQ (0x01ul << 5) /* CAN Abort Request */
#define OVRQ (0x01ul << 6) /* CAN Overload Request */
#define ISS (0x01ul << 7) /* Interrupt Source Status */
#define REC (0xFFul << 16) /* Reception Error Counter */
#define TEC (0xFFul << 24) /* Transmit Error Counter */
/******************************************************************************
* CISR, ISSR, SIER, SIDR, SIMR : CAN Interrupt Source Registers
******************************************************************************/
#define CH0 (0x01ul << 0) /* Interrupt channel 0 */
#define CH1 (0x01ul << 1) /* Interrupt channel 1 */
#define CH2 (0x01ul << 2) /* Interrupt channel 2 */
#define CH3 (0x01ul << 3) /* Interrupt channel 3 */
#define CH4 (0x01ul << 4) /* Interrupt channel 4 */
#define CH5 (0x01ul << 5) /* Interrupt channel 5 */
#define CH6 (0x01ul << 6) /* Interrupt channel 6 */
#define CH7 (0x01ul << 7) /* Interrupt channel 7 */
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