csp.h

IAR 平台ATMEL 的例程, 和说明

/*-----------------------------------------------------------------------------
*   EUROPE TECHNOLOGIES Software Support
*------------------------------------------------------------------------------
* The software is delivered "AS IS" without warranty or condition of any
* kind, either express, implied or statutory. This includes without
* limitation any warranty or condition with respect to merchantability or
* fitness for any particular purpose, or against the infringements of
* intellectual property rights of others.
*------------------------------------------------------------------------------
*
* Processor       : easyCAN4
* File Name       : csp.h
* Description     : Definitions and Structures for easyCan4
* Library Version : 1.00
*
*       +----- (NEW | MODify | ADD | DELete)                                 
*       |                                                                    
*  No   |   When       Who                What               
*-----+---+----------+------------------+--------------------------------------
* 000  NEW  17/07/02   Christophe GARDIN  Creation
*----------------------------------------------------------------------------*/

#ifndef CSP_H
#define CSP_H


/******************************************************************************
* Include Files
******************************************************************************/
#include "csp_types.h"
#include "csp_pwm4c.h"
#include "csp_pmc.h"
#include "csp_cm.h"
#include "csp_gpt.h"
#include "csp_can.h"
#include "csp_st.h"
#include "csp_gic.h"
#include "csp_wt.h"
#include "csp_wd.h"
#include "csp_usart.h"
#include "csp_pdc.h"
#include "csp_amc.h"
#include "csp_adc8c.h"
#include "csp_sfm.h"
#include "csp_pio.h"
#include "csp_spi.h"
#include "csp_capt.h"


/******************************************************************************
****************************** Chip Declaration *******************************
******************************************************************************/
/* Number of Peripherals                                                     */
#define PERIPH_NUMBER   19u

/******************************************************************************
* Peripheral Base Addresses
******************************************************************************/
#define AMC_BASE_ADDRESS      0xFFE00000ul   /* Advanced Memory Controller   */
#define SFM_BASE_ADDRESS      0xFFF00000ul   /* Special Function Module      */
#define WD_BASE_ADDRESS       0xFFFA0000ul   /* WATCHDOG                     */
#define WT_BASE_ADDRESS       0xFFFA4000ul   /* WATCHTIMER                   */
#define USART0_BASE_ADDRESS   0xFFFA8000ul   /* USART0                       */
#define USART1_BASE_ADDRESS   0xFFFAC000ul   /* USART1                       */
#define CAN3_BASE_ADDRESS     0xFFFB0000ul   /* CAN3 (16 channels)           */
#define SPI0_BASE_ADDRESS     0xFFFB4000ul   /* SPI 0                        */
#define CAN1_BASE_ADDRESS     0xFFFB8000ul   /* CAN1 (16 channels)           */
#define CAN2_BASE_ADDRESS     0xFFFBC000ul   /* CAN2 (32 channels)           */
#define ADC0_BASE_ADDRESS     0xFFFC0000ul   /* ADC0 (8 channels)            */
#define ADC1_BASE_ADDRESS     0xFFFC4000ul   /* ADC1 (8 channels)            */
#define GPT0_BASE_ADDRESS     0xFFFC8000ul   /* 16-bit Timer T0 (3 channels) */
#define GPT0CH0_BASE_ADDRESS  0xFFFC8000ul   /* 16-bit Timer T0 channel 0    */
#define GPT0CH1_BASE_ADDRESS  0xFFFC8100ul   /* 16-bit Timer T0 channel 1    */
#define GPT0CH2_BASE_ADDRESS  0xFFFC8200ul   /* 16-bit Timer T0 channel 2    */
#define GPT1_BASE_ADDRESS     0xFFFCC000ul   /* 16-bit Timer T1 (1 channel)  */
#define GPT1CH0_BASE_ADDRESS  0xFFFCC000ul   /* 16-bit Timer T1 channel 0    */
#define PWM_BASE_ADDRESS      0xFFFD0000ul   /* PWM (4 channels)             */
#define CAN0_BASE_ADDRESS     0xFFFD4000ul   /* CAN0 (16 channels)           */
#define UPIO_BASE_ADDRESS     0xFFFD8000ul   /* United PIO Controller        */
#define CAPT0_BASE_ADDRESS    0xFFFDC000ul   /* Capture 0                    */
#define CAPT1_BASE_ADDRESS    0xFFFE0000ul   /* Capture 1                    */
#define ST0_BASE_ADDRESS      0xFFFE4000ul   /* Simple Timer 0               */
#define ST1_BASE_ADDRESS      0xFFFE8000ul   /* Simple Timer 1               */
#define CM_BASE_ADDRESS       0xFFFEC000ul   /* Clock Manager                */
#define PMC_BASE_ADDRESS      0xFFFF4000ul   /* Power Management Controller  */
#define PDC_BASE_ADDRESS      0xFFFF8000ul   /* Peripheral Data Controller   */
#define GIC_BASE_ADDRESS      0xFFFFF000ul   /* Generic Interrupt Controller */


/******************************************************************************
**************************** Interrupt Declaration ****************************
******************************************************************************/

/******************************************************************************
* Interrupt Source
******************************************************************************/
#define FIQ             0ul            /* Fast Interrupt                     */
#define SWIRQ0          1ul            /* Software Interrupt 0               */
#define INT_0           2ul            /* Watchdog Interrupt                 */
#define INT_1           3ul            /* Watch Timer Interrupt              */
#define INT_2           4ul            /* USART0 Interrupt                   */
#define INT_3           5ul            /* USART1 Interrupt                   */
#define INT_4           6ul            /* CAN3 Interrupt                     */
#define INT_5           7ul            /* SPI Interrupt                      */
#define INT_6           8ul            /* CAN1 Interrupt                     */
#define INT_7           9ul            /* CAN2 Interrupt                     */
#define INT_8           10ul           /* ADC0 Interrupt                     */
#define INT_9           11ul           /* ADC1 Interrupt                     */
#define INT_10          12ul           /* GPT0CH0 Interrupt                  */
#define INT_11          13ul           /* GPT0CH1 Interrupt                  */
#define INT_12          14ul           /* GPT0CH2 Interrupt                  */
#define INT_13          15ul           /* GPT1CH0 Interrupt                  */
#define INT_14          16ul           /* PWM Interrupt                      */
#define SWIRQ1          17ul           /* Software Interrupt 1               */
#define SWIRQ2          18ul           /* Software Interrupt 2               */
#define SWIRQ3          19ul           /* Software Interrupt 3               */
#define INT_18          20ul           /* CAN0 Interrupt                     */
#define INT_19          21ul           /* UPIO Interrupt                     */
#define INT_20          22ul           /* CAPT0 Interrupt                    */
#define INT_21          23ul           /* CAPT1 Interrupt                    */
#define INT_22          24ul           /* ST0 Interrupt                      */
#define INT_23          25ul           /* ST1 Interrupt                      */
#define SWIRQ4          26ul           /* Software Interrupt 4               */
#define SWIRQ5          27ul           /* Software Interrupt 5               */
#define EXTIRQ0         28ul           /* External Interrupt 0               */
#define EXTIRQ1         29ul           /* External Interrupt 1               */
#define SWIRQ6          30ul           /* Software Interrupt 6               */
#define SWIRQ7          31ul           /* Software Interrupt 7               */
                        
/******************************************************************************
* GIC Bit 
******************************************************************************/
#define IBIT_FIQ        (0x01ul << 0)  /* Fast Interrupt                     */
#define IBIT_SWIRQ0     (0x01ul << 1)  /* Software Interrupt 0               */
#define IBIT_WD         (0x01ul << 2)  /* Watchdog Interrupt                 */
#define IBIT_WT         (0x01ul << 3)  /* Watch Timer Interrupt              */
#define IBIT_USART0     (0x01ul << 4)  /* USART0 Interrupt                   */
#define IBIT_USART1     (0x01ul << 5)  /* USART1 Interrupt                   */
#define IBIT_CAN3       (0x01ul << 6)  /* CAN3 Interrupt                     */
#define IBIT_SPI        (0x01ul << 7)  /* SPI Interrupt                      */