📄 csp_gpt.h
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/******************************************************************************
* SR, IER, IDR, IMR : GPT Status and Interrupt Registers (Waveform mode)
******************************************************************************/
/* COVFS : Counter Overflow - Same as Capture Mode */
#define CPAS (0x01ul << 2) /* Compare Register A */
#define CPBS (0x01ul << 3) /* Compare Register B */
/* CPCS : Compare Register C - Same as Capture Mode */
/* ETRGS : External Trigger - Same as Capture Mode */
/* TIOBS : TIOB Status - Same as Capture Mode */
/* TIOAS : TIOA Status - Same as Capture Mode */
/* TCLKS : TCLK Status - Same as Capture Mode */
/* SR Register Only */
/* CLKSTA : Clock Status - Same as Capture Mode */
/* MTIOA : TIOA mirror - Same as Capture Mode */
/* MTIOB : TIOB mirror - Same as Capture Mode */
/******************************************************************************
* CV : GPT Counter Value Register
******************************************************************************/
#define CV_MASK (0xFFFFul << 0) /* Counter Value Mask */
/******************************************************************************
* RA : GPT Register A Value
******************************************************************************/
#define RA_MASK (0xFFFFul << 0) /* RA Mask */
/******************************************************************************
* RB : GPT Register B Value
******************************************************************************/
#define RB_MASK (0xFFFFul << 0) /* RB Mask */
/******************************************************************************
* RC : GPT Register C Value
******************************************************************************/
#define RC_MASK (0xFFFFul << 0) /* RC Mask */
/******************************************************************************
* BCR : GPT Block Control Register - 3 Channels Only
******************************************************************************/
/* SWRST : GPT Software Block Reset - Same as CR */
#define TCSYNC (0x01ul << 1) /* Synchronization Bit */
/******************************************************************************
* BMR : GPT Block Mode Register - 3 Channels Only
******************************************************************************/
/* GPT0XC0S : External Clock XC0 Selection */
#define GPT0XC0S (0x03ul << 0) /* GPT0XC0S Mask */
#define TCLK0_XC0 (0x00ul << 0) /* XC0 signal select */
#define NONE_XC0 (0x01ul << 0) /* None signal select */
#define TIOA1_XC0 (0x02ul << 0) /* TIOA1 signal select */
#define TIOA2_XC0 (0x03ul << 0) /* TIOA2 signal select */
/* GPT1XC1S : External Clock XC1 Selection */
#define GPT1XC1S (0x03ul << 2) /* GPT0XC1S Mask */
#define TCLK1_XC1 (0x00ul << 2) /* XC1 signal select */
#define NONE_XC1 (0x01ul << 2) /* None signal select */
#define TIOA0_XC1 (0x02ul << 2) /* TIOA0 signal select */
#define TIOA2_XC1 (0x03ul << 2) /* TIOA2 signal select */
/* GPT2XC2S : External Clock XC2 Selection */
#define GPT2XC2S (0x03ul << 4) /* GPT0XC2S Mask */
#define TCLK2_XC2 (0x00ul << 4) /* XC2 signal select */
#define NONE_XC2 (0x01ul << 4) /* None signal select */
#define TIOA0_XC2 (0x02ul << 4) /* TIOA0 signal select */
#define TIOA1_XC2 (0x03ul << 4) /* TIOA1 signal select */
/******************************************************************************
* TSTC : GPT Test Control Register in test mode
******************************************************************************/
#define LDCT (0x01ul << 0) /* Load Timer Counter (GPT1C) */
#define LDCT0 (0x01ul << 0) /* Load Timer 0 Counter (GPT3C) */
#define LDCT1 (0x01ul << 1) /* Load Timer 1 Counter (GPT3C) */
#define LDCT2 (0x01ul << 2) /* Load Timer 2 Counter (GPT3C) */
/******************************************************************************
* TSTM : GPT Test Mode Register in test mode
******************************************************************************/
#define OCLKEN (0x01ul << 0) /* Output Clock on TIOB0 (GPT1C) */
#define OCLKEN0 (0x01ul << 0) /* Output Clock on TIOB0 for Timer 0 (GPT3C) */
#define OCLKEN1 (0x01ul << 1) /* Output Clock on TIOB0 for Timer 1 (GPT3C) */
#define OCLKEN2 (0x01ul << 2) /* Output Clock on TIOB0 for Timer 2 (GPT3C) */
/******************************************************************************
*************************** GPT Macros Definition *****************************
******************************************************************************/
/* PER, PDR, PSR : GPT PIO Registers */
#define CSP_GPT_SET_PER(gpt, val) ((gpt)->PER = (val)) /* Enable */
#define CSP_GPT_SET_PDR(gpt, val) ((gpt)->PDR = (val)) /* Disable */
#define CSP_GPT_GET_PSR(gpt) ((gpt)->PSR) /* Status */
/* OER, ODR, OSR : GPT Output Registers */
#define CSP_GPT_SET_OER(gpt, val) ((gpt)->OER = (val)) /* Enable */
#define CSP_GPT_SET_ODR(gpt, val) ((gpt)->ODR = (val)) /* Disable */
#define CSP_GPT_GET_OSR(gpt) ((gpt)->OSR) /* Status */
/* SODR, CODR, ODSR, PDSR : GPT Output Data Registers */
#define CSP_GPT_SET_SODR(gpt, val) ((gpt)->SODR = (val)) /* Set */
#define CSP_GPT_SET_CODR(gpt, val) ((gpt)->CODR = (val)) /* Clear */
#define CSP_GPT_GET_ODSR(gpt) ((gpt)->ODSR) /* Status */
#define CSP_GPT_GET_PDSR(gpt) ((gpt)->PDSR) /* Pin Status */
/* MDER, MDDR, MDSR : GPT Multi-Driver Registers */
#define CSP_GPT_SET_MDER(gpt, val) ((gpt)->MDER = (val)) /* Enable */
#define CSP_GPT_SET_MDDR(gpt, val) ((gpt)->MDDR = (val)) /* Disable */
#define CSP_GPT_GET_MDSR(gpt) ((gpt)->MDSR) /* Status */
/* ECR, DCR, PMSR : GPT Power Management Registers */
#define CSP_GPT_SET_ECR(gpt, val) ((gpt)->ECR = (val)) /* Enable */
#define CSP_GPT_SET_DCR(gpt, val) ((gpt)->DCR = (val)) /* Disable */
#define CSP_GPT_GET_PMSR(gpt) ((gpt)->PMSR) /* Status */
/* CR : GPT Control Register */
#define CSP_GPT_SET_CR(gpt, val) ((gpt)->CR = (val))
/* MR : GPT Mode Register */
#define CSP_GPT_GET_MR(gpt) ((gpt)->MR)
#define CSP_GPT_SET_MR(gpt, mode) ((gpt)->MR = (mode))
/* SR : GPT Status Register */
#define CSP_GPT_GET_SR(gpt) ((gpt)->SR)
/* IER, IDR, IMR : GPT Interrupt Registers */
#define CSP_GPT_SET_IER(gpt, val) ((gpt)->IER = (val)) /* Enable */
#define CSP_GPT_SET_IDR(gpt, val) ((gpt)->IDR = (val)) /* Disable */
#define CSP_GPT_GET_IMR(gpt) ((gpt)->IMR) /* Mask */
/* CV : GPT Counter Value Register */
#define CSP_GPT_GET_CV(gpt) ((gpt)->CV)
/* RA : GPT Capture - Compare Register A */
#define CSP_GPT_GET_RA(gpt) ((gpt)->RA)
#define CSP_GPT_SET_RA(gpt, val) ((gpt)->RA = (val))
/* RB : GPT Capture - Compare Register B */
#define CSP_GPT_GET_RB(gpt) ((gpt)->RB)
#define CSP_GPT_SET_RB(gpt, val) ((gpt)->RB = (val))
/* RC : GPT Compare Register C */
#define CSP_GPT_GET_RC(gpt) ((gpt)->RC)
#define CSP_GPT_SET_RC(gpt, val) ((gpt)->RC = (val))
/* BCR : GPT Block Control Register - 3 Channels Only */
#define CSP_GPT_SET_BCR(gpt, val) ((gpt)->BCR = (val))
/* BMR : GPT Block Mode Register - 3 Channels Only */
#define CSP_GPT_GET_BMR(gpt) ((gpt)->BMR)
#define CSP_GPT_SET_BMR(gpt, val) ((gpt)->BMR = (val))
/* TSTC : GPT Test Control Register in Test Mode */
#define CSP_GPT_SET_TSTC(gpt, val) ((gpt)->TSTC = (val))
/* TSTM : GPT Test Mode Register in Test Mode */
#define CSP_GPT_GET_TSTM(gpt) ((gpt)->TSTM)
#define CSP_GPT_SET_TSTM(gpt, val) ((gpt)->TSTM = (val))
/******************************************************************************
********************* GPT External Functions Declaration **********************
******************************************************************************/
extern void CSP_GPTInit(CSP_GPT_T *const gpt, U32_T mode, U16_T *reg_value);
extern void CSP_GPTClose(CSP_GPT_T *const gpt);
extern void CSP_GPTConfigInterrupt(CSP_GPT_T *const gpt, U32_T int_mode, U32_T int_mask, U32_T callback);
extern void CSP_GPTEnable(CSP_GPT_T *const gpt);
extern void CSP_GPTDisable(CSP_GPT_T *const gpt);
extern void CSP_GPTPioInit(CSP_GPT_T *const gpt, U32_T pio_mask, U32_T output_pio);
extern U32_T CSP_GPTPioGetStatus(CSP_GPT_T *const gpt);
extern void CSP_GPTPioSet(CSP_GPT_T *const gpt, U32_T pio_mask);
extern void CSP_GPTPioClear(CSP_GPT_T *const gpt, U32_T pio_mask);
#endif /* CSP_GPT_H */
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