csp_gpt.h

IAR 平台ATMEL 的例程, 和说明

* CR : GPT Control Register
******************************************************************************/
#define SWRST           (0x01ul << 0)  /* GPT Software Reset                 */
#define CLKEN           (0x01ul << 1)  /* Counter Clock Enable               */
#define CLKDIS          (0x01ul << 2)  /* Counter Clock Disable              */
#define SWTRG           (0x01ul << 3)  /* Software Trigger                   */

/******************************************************************************
* MR : GPT Mode Register (Capture mode)
******************************************************************************/
/* CLKS : Clock Source                                                       */
#define CLKS            (0x07ul << 0)  /* CLKS Mask                          */
#define CLKS_MCK2       (0x00ul << 0)  /* MCK/2                              */
#define CLKS_MCK8       (0x01ul << 0)  /* MCK/8                              */
#define CLKS_MCK32      (0x02ul << 0)  /* MCK/32                             */
#define CLKS_MCK128     (0x03ul << 0)  /* MCK/128                            */
#define CLKS_MCK1024    (0x04ul << 0)  /* MCK/1024                           */
#define CLKS_XC0        (0x05ul << 0)  /* External XC0                       */
#define CLKS_XC1        (0x06ul << 0)  /* External XC1                       */
#define CLKS_XC2        (0x07ul << 0)  /* External XC2                       */

/* CLKI : Clock Inverter                                                     */
#define CLKINV          (0x01ul << 3)

/* BURST : Burst Signal                                                      */
#define BURST           (0x03ul << 4)  /* BURST Mask                         */
#define BURST_NONE      (0x00ul << 4)  /* No signal selected for burst       */
#define BURST_XC0       (0x01ul << 4)  /* XC0 selected for burst             */
#define BURST_XC1       (0x02ul << 4)  /* XC1 selected for burst             */
#define BURST_XC2       (0x03ul << 4)  /* XC2 selected for burst             */

/* LDBSTOP : Counter clock stopped with RB Loading                           */
#define LDBSTOP         (0x01ul << 6)

/* LDBDIS : Counter clock disable with RB Loading                            */
#define LDBDIS          (0x01ul << 7)

/* ETRGEDG : External Trigger Edge                                           */
#define ETRGEDG         (0x03ul << 8)  /* ETRGEDG Mask                       */
#define ETRGEDG_NONE    (0x00ul << 8)  /* No external trigger                */
#define ETRGEDG_RISING  (0x01ul << 8)  /* Rising edge trigger                */
#define ETRGEDG_FALLING (0x02ul << 8)  /* Falling edge trigger               */
#define ETRGEDG_EACH    (0x03ul << 8)  /* Each edge trigger                  */

/* ABETRG : TIOA or TIOB External Trigger                                    */
#define ABETRG          (0x01ul << 10) /* ABETRG Mask                        */
#define ABETRG_TIOA     (0x01ul << 10) /* TIOA selected for external trigger */
#define ABETRG_TIOB     (0x00ul << 10) /* TIOB selected for external trigger */
                               
/* CPCTRG : RC Compare Trigger Enable                                        */
#define CPCTRG          (0x01ul << 14)

/* WAVE = CAPT_ENA : Capture Mode is enabled                                 */
#define WAVE            (0x01ul << 15) /* WAVE Mask                          */
#define CAPT_ENA        (0x00ul << 15) /* Capture Mode                       */
#define WAVE_ENA        (0x01ul << 15) /* Waveform Mode                      */

/* LDRA : Load RA                                                            */
#define LDRA            (0x03ul << 16) /* LDRA Mask                          */
#define LDRA_NONE       (0x00ul << 16) /* No external trigger selected       */
#define LDRA_RISING     (0x01ul << 16) /* Rising edge on TIOA                */
#define LDRA_FALLING    (0x02ul << 16) /* Falling edge on TIOA               */
#define LDRA_EACH       (0x03ul << 16) /* Each edge on TIOA                  */

/* LDRB : Load RB                                                            */
#define LDRB            (0x03ul << 18) /* LRRB Mask                          */
#define LDRB_NONE       (0x00ul << 18) /* No external trigger selected       */
#define LDRB_RISING     (0x01ul << 18) /* Rising edge on TIOA                */
#define LDRB_FALLING    (0x02ul << 18) /* Falling edge on TIOA               */
#define LDRB_EACH       (0x03ul << 18) /* Each edge on TIOA                  */

/******************************************************************************
* MR : Mode Register (Waveform mode)
******************************************************************************/
/* CLKS  : Clock source   - Same as Capture Mode                             */
/* CLKI  : Clock inverter - Same as Capture Mode                             */
/* BURST : Burst signal   - Same as Capture Mode                             */

/* CPCSTOP : Compare RC Stops the counter                                    */
#define CPCSTOP         (0x01ul << 6)  /* CPCSTOP Mask                       */
#define CPCSTOP_DIS     (0x00ul << 6)  /* Counter is not stopped when equal condition on RC    */
#define CPCSTOP_ENA     (0x01ul << 6)  /* Counter is stopped when equal condition on RC        */

/* CPCDIS : Compare RC Disables Clock                                        */
#define CPCSDIS         (0x01ul << 7)  /* CPCSDIS Mask                       */
#define CPCSDIS_DIS     (0x00ul << 7)  /* Counter clock is disables when equal condition on RC */
#define CPCSDIS_ENA     (0x01ul << 7)  /* Counter clock disables when equal condition on RC    */

/* EEVTEDG : External Event Edge                                             */
#define EEVTEDG         (0x03ul << 8)  /* EEVTEDG Mask                       */
#define EEVTEDG_NONE    (0x00ul << 8)  /* No external event edge             */
#define EEVTEDG_RISING  (0x01ul << 8)  /* Rising event edge                  */
#define EEVTEDG_FALLING (0x02ul << 8)  /* Falling event edge                 */ 
#define EEVTEDG_EACH    (0x03ul << 8)  /* Each event edge                    */

/* EEVT : External Event                                                     */
#define EEVT            (0x03ul << 10) /* EEVT Mask                          */
#define EEVT_TIOB       (0x00ul << 10) /* TIOB External Trigger              */
#define EEVT_XC0        (0x01ul << 10) /* XC0 External Trigger               */
#define EEVT_XC1        (0x02ul << 10) /* XC1 External Trigger               */
#define EEVT_XC2        (0x03ul << 10) /* XC2 External Trigger               */

/* ENETRG : Enable External Trigger                                          */
#define ENETRG          (0x01ul << 12)

/* CPCTRG : RC compare trigger enable - Same as Capture Mode                 */
/* WAVE = WAVE_ENA : Waveform mode is enable                                 */

/* ACPA : RA Compare Effect on TIOA                                          */
#define ACPA            (0x03ul << 16) /* ACPA Mask                          */
#define ACPA_NONE       (0x00ul << 16) /* No effect on TIOA output           */
#define ACPA_SET        (0x01ul << 16) /* SET TIOA output                    */
#define ACPA_CLEAR      (0x02ul << 16) /* Clear TIOA output                  */
#define ACPA_TOGGLE     (0x03ul << 16) /* Toggle TIOA output                 */

/* ACPC : RC Compare Effect on TIOA                                          */
#define ACPC            (0x03ul << 18) /* ACPC Mask                          */
#define ACPC_NONE       (0x00ul << 18) /* No effect on TIOA output           */
#define ACPC_SET        (0x01ul << 18) /* SET TIOA output                    */
#define ACPC_CLEAR      (0x02ul << 18) /* Clear TIOA output                  */
#define ACPC_TOGGLE     (0x03ul << 18) /* Toggle TIOA output                 */

/* AEEVT : External Event Effect on TIOA                                     */
#define AEEVT           (0x03ul << 20) /* AEEVT Mask                         */
#define AEEVT_NONE      (0x00ul << 20) /* No effect on TIOA output           */
#define AEEVT_SET       (0x01ul << 20) /* SET TIOA output                    */
#define AEEVT_CLEAR     (0x02ul << 20) /* Clear TIOA output                  */
#define AEEVT_TOGGLE    (0x03ul << 20) /* Toggle TIOA output                 */

/* ASWTRG : Software Trigger Effect on TIOA                                  */
#define ASWTRG          (0x03ul << 22) /* ASWTRG Mask                        */
#define ASWTRG_NONE     (0x00ul << 22) /* No effect on TIOA output           */
#define ASWTRG_SET      (0x01ul << 22) /* SET TIOA output                    */
#define ASWTRG_CLEAR    (0x02ul << 22) /* Clear TIOA output                  */
#define ASWTRG_TOGGLE   (0x03ul << 22) /* Toggle TIOA output                 */

/* BCPB : RB Compare Effect on TIOB                                          */
#define BCPB            (0x03ul << 24) /* BCPB Mask                          */
#define BCPB_NONE       (0x00ul << 24) /* No effect on TIOB output           */
#define BCPB_SET        (0x01ul << 24) /* SET TIOB output                    */
#define BCPB_CLEAR      (0x02ul << 24) /* Clear TIOB output                  */
#define BCPB_TOGGLE     (0x03ul << 24) /* Toggle TIOB output                 */

/* BCPC : RC Compare Effect on TIOB                                          */
#define BCPC            (0x03ul << 26) /* BCPC Mask                          */
#define BCPC_NONE       (0x00ul << 26) /* No effect on TIOB output           */
#define BCPC_SET        (0x01ul << 26) /* SET TIOB output                    */
#define BCPC_CLEAR      (0x02ul << 26) /* Clear TIOB output                  */
#define BCPC_TOGGLE     (0x03ul << 26) /* Toggle TIOB output                 */

/* BEEVT : External Event Effect on TIOB                                     */
#define BEEVT           (0x03ul << 28) /* BEEVT Mask                         */
#define BEEVT_NONE      (0x00ul << 28) /* No effect on TIOB output           */
#define BEEVT_SET       (0x01ul << 28) /* SET TIOB output                    */
#define BEEVT_CLEAR     (0x02ul << 28) /* Clear TIOB output                  */
#define BEEVT_TOGGLE    (0x03ul << 28) /* Toggle TIOB output                 */

/* BSWTRG : Software Trigger Effect on TIOB                                  */
#define BSWTRG          (0x03ul << 30) /* BSWTRG Mask                        */
#define BSWTRG_NONE     (0x00ul << 30) /* No effect on TIOB output           */
#define BSWTRG_SET      (0x01ul << 30) /* SET TIOB output                    */
#define BSWTRG_CLEAR    (0x02ul << 30) /* Clear TIOB output                  */
#define BSWTRG_TOGGLE   (0x03ul << 30) /* Toggle TIOB output                 */

/******************************************************************************
* SR, IER, IDR, IMR : GPT Status and Interrupt Registers (capture mode)
******************************************************************************/
#define COVFS           (0x01ul << 0)  /* Counter overflow                   */
#define LOVRS           (0x01ul << 1)  /* Load overrun                       */
#define CPCS            (0x01ul << 4)  /* Compare Register C                 */
#define LDRAS           (0x01ul << 5)  /* Load Register A                    */
#define LDRBS           (0x01ul << 6)  /* Load Register B                    */
#define ETRGS           (0x01ul << 7)  /* External Trigger                   */
#define TIOBS           (0x01ul << 16) /* TIOB Status                        */
#define TIOAS           (0x01ul << 17) /* TIOA Status                        */
#define TCLKS           (0x01ul << 18) /* TCLK Status                        */

/* SR Register Only                                                          */
#define CLKSTA          (0x01ul << 8)  /* Clock Status                       */
#define MTIOA           (0x01ul << 9)  /* TIOA Mirror                        */
#define MTIOB           (0x01ul << 10) /* TIOB Mirror                        */