📄 csp_gpt.h
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/*-----------------------------------------------------------------------------
* EUROPE TECHNOLOGIES Software Support
*------------------------------------------------------------------------------
* The software is delivered "AS IS" without warranty or condition of any
* kind, either express, implied or statutory. This includes without
* limitation any warranty or condition with respect to merchantability or
* fitness for any particular purpose, or against the infringements of
* intellectual property rights of others.
*------------------------------------------------------------------------------
*
* File Name : csp_gpt.h
* Description : Definitions, Macros and function declarations for
* General Purpose Timer module
* Library Version : 2.00
* Module Version : 1.XX
*
* +----- (NEW | MODify | ADD | DELete)
* |
* No | When Who What
*-----+---+----------+------------------+--------------------------------------
* 000 NEW 01/05/99 Patrice VILCHEZ Creation
* 001 MOD 01/04/01 Olivier MAZUYER Clean up
* 002 MOD 08/06/01 Frederic SAMSON Clean Up
* 003 MOD 25/10/01 Christophe GARDIN Clean Up
*----------------------------------------------------------------------------*/
#ifndef CSP_GPT_H
#define CSP_GPT_H
/******************************************************************************
************************** GPT Structure Definition ***************************
******************************************************************************/
/* Physical Timer Definition */
#define GPT_ONE_CHANNEL 1u
#define GPT_THREE_CHANNEL 3u
/******************************************************************************
* GPT Channel Structure
******************************************************************************/
/*******************************************************************************
Type: CSP_GPT_T
Description: GPT Channel Structure
Fields:
- 创CSP_REGISTER_T创 PER : PIO Enable Register
- 创CSP_REGISTER_T创 PDR : PIO Disable Register
- 创CSP_REGISTER_T创 PSR : PIO Status Register
- 创CSP_REGISTER_T创 ReservedA :
- 创CSP_REGISTER_T创 OER : Output Enable Register
- 创CSP_REGISTER_T创 ODR : Output Disable Register
- 创CSP_REGISTER_T创 OSR : Output Status Register
- 创CSP_REGISTER_T创 ReservedB[5] :
- 创CSP_REGISTER_T创 SODR : Set Output Data Register
- 创CSP_REGISTER_T创 CODR : Clear Output Data Register
- 创CSP_REGISTER_T创 ODSR : Output Data Status Register
- 创CSP_REGISTER_T创 PDSR : Pin Data Status Register
- 创CSP_REGISTER_T创 MDER : Multi-Driver Enable Register
- 创CSP_REGISTER_T创 MDDR : Multi-Driver Disable Register
- 创CSP_REGISTER_T创 MDSR : Multi-Driver Status Register
- 创CSP_REGISTER_T创 ReservedC :
- 创CSP_REGISTER_T创 ECR : Enable Clock Register
- 创CSP_REGISTER_T创 DCR : Disable Clock Register
- 创CSP_REGISTER_T创 PMSR : Power Management Status Register
- 创CSP_REGISTER_T创 ReservedD :
- 创CSP_REGISTER_T创 CR : Control Register
- 创CSP_REGISTER_T创 MR : Mode Register
- 创CSP_REGISTER_T创 ReservedE[2] :
- 创CSP_REGISTER_T创 SR : Status Register
- 创CSP_REGISTER_T创 IER : Interrupt Enable Register
- 创CSP_REGISTER_T创 IDR : Interrupt Disable Register
- 创CSP_REGISTER_T创 IMR : Interrupt Mask Register
- 创CSP_REGISTER_T创 CV : Counter value Register
- 创CSP_REGISTER_T创 RA : Register A
- 创CSP_REGISTER_T创 RB : Register B
- 创CSP_REGISTER_T创 RC : Register C
- 创CSP_REGISTER_T创 ReservedF[28] :
*******************************************************************************/
typedef struct
{
CSP_REGISTER_T PER; /* PIO Enable Register */
CSP_REGISTER_T PDR; /* PIO Disable Register */
CSP_REGISTER_T PSR; /* PIO Status Register */
CSP_REGISTER_T ReservedA;
CSP_REGISTER_T OER; /* Output Enable Register */
CSP_REGISTER_T ODR; /* Output Disable Register */
CSP_REGISTER_T OSR; /* Output Status Register */
CSP_REGISTER_T ReservedB[5];
CSP_REGISTER_T SODR; /* Set Output Data Register */
CSP_REGISTER_T CODR; /* Clear Output Data Register */
CSP_REGISTER_T ODSR; /* Output Data Status Register */
CSP_REGISTER_T PDSR; /* Pin Data Status Register */
CSP_REGISTER_T MDER; /* Multi-Driver Enable Register */
CSP_REGISTER_T MDDR; /* Multi-Driver Disable Register */
CSP_REGISTER_T MDSR; /* Multi-Driver Status Register */
CSP_REGISTER_T ReservedC;
CSP_REGISTER_T ECR; /* Enable Clock Register */
CSP_REGISTER_T DCR; /* Disable Clock Register */
CSP_REGISTER_T PMSR; /* Power Management Status Register */
CSP_REGISTER_T ReservedD;
CSP_REGISTER_T CR; /* Control Register */
CSP_REGISTER_T MR; /* Mode Register */
CSP_REGISTER_T ReservedE[2];
CSP_REGISTER_T SR; /* Status Register */
CSP_REGISTER_T IER; /* Interrupt Enable Register */
CSP_REGISTER_T IDR; /* Interrupt Disable Register */
CSP_REGISTER_T IMR; /* Interrupt Mask Register */
CSP_REGISTER_T CV; /* Counter value Register */
CSP_REGISTER_T RA; /* Register A */
CSP_REGISTER_T RB; /* Register B */
CSP_REGISTER_T RC; /* Register C */
CSP_REGISTER_T ReservedF[28];
} CSP_GPT_T;
/******************************************************************************
* GPT 1 Channel Structure
******************************************************************************/
/*******************************************************************************
Type: CSP_GPT1C_T
Description: GPT 1 Channel Structure
Fields:
- 创CSP_GPT_T创 CHANNEL[GPT_ONE_CHANNEL] : GPT Channel
- 创CSP_REGISTER_T创 ReservedA[192] :
- 创CSP_REGISTER_T创 TSTC : Test Control Register
- 创CSP_REGISTER_T创 TSTM : Test Mode Register
*******************************************************************************/
typedef struct
{
CSP_GPT_T CHANNEL[GPT_ONE_CHANNEL]; /* GPT Channel */
CSP_REGISTER_T ReservedA[192];
CSP_REGISTER_T TSTC; /* Test Control Register */
CSP_REGISTER_T TSTM; /* Test Mode Register */
} CSP_GPT1C_T;
/******************************************************************************
* GPT 3 Channels Structure
******************************************************************************/
/*******************************************************************************
Type: CSP_GPT3C_T
Description: GPT 3 Channels Structure
Fields:
- 创CSP_GPT_T创 CHANNEL[GPT_THREE_CHANNEL] : GPT Channel
- 创CSP_REGISTER_T创 BCR : Block Control Register
- 创CSP_REGISTER_T创 BMR : Clock Mode Register
- 创CSP_REGISTER_T创 ReservedA[62] :
- 创CSP_REGISTER_T创 TSTC : Test Control Register
- 创CSP_REGISTER_T创 TSTM : Test Mode Register
*******************************************************************************/
typedef struct
{
CSP_GPT_T CHANNEL[GPT_THREE_CHANNEL]; /* GPT Channel */
CSP_REGISTER_T BCR; /* Block Control Register */
CSP_REGISTER_T BMR; /* Clock Mode Register */
CSP_REGISTER_T ReservedA[62];
CSP_REGISTER_T TSTC; /* Test Control Register */
CSP_REGISTER_T TSTM; /* Test Mode Register */
} CSP_GPT3C_T;
/******************************************************************************
************************** GPT Registers Definition ***************************
******************************************************************************/
/******************************************************************************
* PER, PDR, PSR, OER, ODR, OSR, :
* SODR, CODR, ODSR, PDSR, MDER, MDDR : GPT PIO Registers, Status Register and
* MDSR, SR, IER, IDR, IMR : Interrupt Registers
******************************************************************************/
#define TIOB (0x01ul << 16) /* TIOB */
#define TIOA (0x01ul << 17) /* TIOA */
#define TCLK (0x01ul << 18) /* TCLK */
/******************************************************************************
* ECR, DCR, PMSR : GPT Power Management Registers
******************************************************************************/
#define TIMER (0x01ul << 1) /* GPT Clock */
/******************************************************************************
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