📄 csp_usart.h
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/*-----------------------------------------------------------------------------
* EUROPE TECHNOLOGIES Software Support
*------------------------------------------------------------------------------
* The software is delivered "AS IS" without warranty or condition of any
* kind, either express, implied or statutory. This includes without
* limitation any warranty or condition with respect to merchantability or
* fitness for any particular purpose, or against the infringements of
* intellectual property rights of others.
*------------------------------------------------------------------------------
*
* File Name : csp_usart.h
* Description : Definitions, Macros and function declarations for
* Universal Synchronous/Asynchronous Receiver/Transmitter module
* Library Version : 2.00
* Module Version : 1.XX
*
* +----- (NEW | MODify | ADD | DELete)
* |
* No | When Who What
*-----+---+----------+------------------+--------------------------------------
* 000 NEW 01/05/99 Patrice VILCHEZ Creation
* 001 MOD 01/04/01 Olivier MAZUYER Clean up
* 002 MOD 08/06/01 Frederic SAMSON Clean Up
* 003 MOD 22/10/01 Christophe GARDIN Clean Up
*----------------------------------------------------------------------------*/
#ifndef CSP_USART_H
#define CSP_USART_H
/******************************************************************************
************************ USART Structure Definition ***************************
******************************************************************************/
/*******************************************************************************
Type: CSP_USART_T
Description: USART Structure Definition
Fields:
- 创CSP_REGISTER_T创 PER : PIO Enable Register
- 创CSP_REGISTER_T创 PDR : PIO Disable Register
- 创CSP_REGISTER_T创 PSR : PIO Status Register
- 创CSP_REGISTER_T创 ReservedA :
- 创CSP_REGISTER_T创 OER : Output Enable Register
- 创CSP_REGISTER_T创 ODR : Output Disable Register
- 创CSP_REGISTER_T创 OSR : Output Status Register
- 创CSP_REGISTER_T创 ReservedB[5] :
- 创CSP_REGISTER_T创 SODR : Set Output Data Register
- 创CSP_REGISTER_T创 CODR : Clear Output Data Register
- 创CSP_REGISTER_T创 ODSR : Output Data Status Register
- 创CSP_REGISTER_T创 PDSR : Pin Data Status Register
- 创CSP_REGISTER_T创 MDER : Multi-Driver Enable Register
- 创CSP_REGISTER_T创 MDDR : Multi-Driver Disable Register
- 创CSP_REGISTER_T创 MDSR : Multi-Driver Status Register
- 创CSP_REGISTER_T创 ReservedC :
- 创CSP_REGISTER_T创 ECR : Enable Clock Register
- 创CSP_REGISTER_T创 DCR : Disable Clock Register
- 创CSP_REGISTER_T创 PMSR : Power Management Status Register
- 创CSP_REGISTER_T创 ReservedD :
- 创CSP_REGISTER_T创 CR : Control Register
- 创CSP_REGISTER_T创 MR : Mode Register
- 创CSP_REGISTER_T创 ReservedE[2] :
- 创CSP_REGISTER_T创 SR : Status Register
- 创CSP_REGISTER_T创 IER : Interrupt Enable Register
- 创CSP_REGISTER_T创 IDR : Interrupt Disable Register
- 创CSP_REGISTER_T创 IMR : Interrupt Mask Register
- 创CSP_REGISTER_T创 RHR : Receiver Holding Register
- 创CSP_REGISTER_T创 THR : Transmit Holding Register
- 创CSP_REGISTER_T创 BRGR : Baud Rate Generator Register
- 创CSP_REGISTER_T创 RTOR : Receiver Time-out Register
- 创CSP_REGISTER_T创 TTGR : Transmitter Time-guard Register
*******************************************************************************/
typedef struct
{
CSP_REGISTER_T PER; /* PIO Enable Register */
CSP_REGISTER_T PDR; /* PIO Disable Register */
CSP_REGISTER_T PSR; /* PIO Status Register */
CSP_REGISTER_T ReservedA;
CSP_REGISTER_T OER; /* Output Enable Register */
CSP_REGISTER_T ODR; /* Output Disable Register */
CSP_REGISTER_T OSR; /* Output Status Register */
CSP_REGISTER_T ReservedB[5];
CSP_REGISTER_T SODR; /* Set Output Data Register */
CSP_REGISTER_T CODR; /* Clear Output Data Register */
CSP_REGISTER_T ODSR; /* Output Data Status Register */
CSP_REGISTER_T PDSR; /* Pin Data Status Register */
CSP_REGISTER_T MDER; /* Multi-Driver Enable Register */
CSP_REGISTER_T MDDR; /* Multi-Driver Disable Register */
CSP_REGISTER_T MDSR; /* Multi-Driver Status Register */
CSP_REGISTER_T ReservedC;
CSP_REGISTER_T ECR; /* Enable Clock Register */
CSP_REGISTER_T DCR; /* Disable Clock Register */
CSP_REGISTER_T PMSR; /* Power Management Status Register*/
CSP_REGISTER_T ReservedD;
CSP_REGISTER_T CR; /* Control Register */
CSP_REGISTER_T MR; /* Mode Register */
CSP_REGISTER_T ReservedE[2];
CSP_REGISTER_T SR; /* Status Register */
CSP_REGISTER_T IER; /* Interrupt Enable Register */
CSP_REGISTER_T IDR; /* Interrupt Disable Register */
CSP_REGISTER_T IMR; /* Interrupt Mask Register */
CSP_REGISTER_T RHR; /* Receiver Holding Register */
CSP_REGISTER_T THR; /* Transmit Holding Register */
CSP_REGISTER_T BRGR; /* Baud Rate Generator Register */
CSP_REGISTER_T RTOR; /* Receiver Time-out Register */
CSP_REGISTER_T TTGR; /* Transmitter Time-guard Register */
} CSP_USART_T;
/******************************************************************************
************************* USART Registers Definition **************************
******************************************************************************/
/******************************************************************************
* PER, PDR, PSR, OER, ODR, OSR, :
* SODR, CODR, ODSR, PDSR, MDER, MDDR : USART PIO Registers, Status Registers and
* MDSR, SR, IER, IDR, IMR : Interrupt Registers
******************************************************************************/
#define SCK (0x01ul << 16) /* SCK */
#define TXD (0x01ul << 17) /* TXD */
#define RXD (0x01ul << 18) /* RXD */
/******************************************************************************
* ECR, DCR, PMSR : USART Power Management Registers
******************************************************************************/
#define PIO (0x01ul << 0) /* PIO Clock */
#define USART (0x01ul << 1) /* USART Clock */
/******************************************************************************
* CR : USART Control Register
******************************************************************************/
#define SWRST (0x01ul << 0) /* Software Reset */
#define RSTRX (0x01ul << 2) /* Reset Receiver */
#define RSTTX (0x01ul << 3) /* Reset Transmitter */
#define RXEN (0x01ul << 4) /* Receiver Enable */
#define RXDIS (0x01ul << 5) /* Receiver Disable */
#define TXEN (0x01ul << 6) /* Transmitter Enable */
#define TXDIS (0x01ul << 7) /* Transmitter Disable */
#define RSTSTA (0x01ul << 8) /* Reset Status Bits */
#define STTBRK (0x01ul << 9) /* Start Break */
#define STPBRK (0x01ul << 10) /* Stop Break */
#define STTTO (0x01ul << 11) /* Start Time-out */
#define SENDA (0x01ul << 12) /* Send Address */
/******************************************************************************
* MR : USART Mode Register
******************************************************************************/
/* USCLKS : Clock Selection */
#define USCLKS (0x03ul << 4) /* USCLKS Mask */
#define USCLKS_MCKI (0x00ul << 4) /* Core Clock (MCKI) */
#define USCLKS_MCKI_8 (0x01ul << 4) /* Core Clock / 8 (MCKI/8) */
#define USCLKS_SCK (0x02ul << 4) /* External Clock (SCK) */
/* CHRL : Character Length */
#define CHRL (0x03ul << 6) /* CHRL Mask */
#define CHRL_5 (0x00ul << 6) /* Five bits length */
#define CHRL_6 (0x01ul << 6) /* Six bits length */
#define CHRL_7 (0x02ul << 6) /* Seven bits length */
#define CHRL_8 (0x03ul << 6) /* Height bits length */
/* SYNC : Synchronous Mode Select */
#define SYNC (0x01ul << 8) /* Synchronous mode */
#define ASYNC (0x00ul << 8) /* Asynchronous mode */
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