csp_pwm4c.h

IAR 平台ATMEL 的例程, 和说明

/*-----------------------------------------------------------------------------
*   EUROPE TECHNOLOGIES Software Support
*------------------------------------------------------------------------------
* The software is delivered "AS IS" without warranty or condition of any
* kind, either express, implied or statutory. This includes without
* limitation any warranty or condition with respect to merchantability or
* fitness for any particular purpose, or against the infringements of
* intellectual property rights of others.
*------------------------------------------------------------------------------
*
* File Name       : csp_pwm4c.h
* Description     : Definitions, Macros and function declarations for
*                   Pulse Width Modulator 4 channels module
* Library Version : 2.00
* Module Version  : 1.XX
*
*       +----- (NEW | MODify | ADD | DELete)                                 
*       |                                                                    
*  No   |   When       Who                What               
*-----+---+----------+------------------+--------------------------------------
* 000  NEW  01/05/99   Patrice VILCHEZ    Creation
* 001  MOD  01/04/01   Olivier MAZUYER    Clean up
* 002  MOD  08/06/01   Frederic SAMSON    Clean Up 
* 003  MOD  25/10/01   Christophe GARDIN  Clean Up
* 004  MOD  28/03/02   Christophe GARDIN  Add PRESCAL macros 
* 005  MOD  21/11/02   Bruno SALLE		  Modification for SmartCAN1 : add PIO block
*----------------------------------------------------------------------------*/

#ifndef CSP_PWM4C_H
#define CSP_PWM4C_H


/******************************************************************************
************************ PWM4C Structure Definition ***************************
******************************************************************************/

/* Number of PWM Channels                                                    */
#define NB_PWM_CHANNEL  4u

/******************************************************************************
* PWM Channel Structure
******************************************************************************/

/*******************************************************************************
Type: CSP_PWM_CHANNEL_T
Description: PWM Channel Structure Definition
Fields:
- 创CSP_REGISTER_T创  DLY :             Delay Register 
- 创CSP_REGISTER_T创  PUL :             Pulse Register 
*******************************************************************************/
typedef struct
{
   CSP_REGISTER_T  DLY;             /* Delay Register                        */
   CSP_REGISTER_T  PUL;             /* Pulse Register                        */
} CSP_PWM_CHANNEL_T;


/******************************************************************************
* PWM 4 Channels Structure
******************************************************************************/

/*******************************************************************************
Type: CSP_PWM4C_T
Description: PWM Structure Definition
Fields:
- 创CSP_REGISTER_T创  PER :                PIO Enable  Register          	     
- 创CSP_REGISTER_T创  PDR :                PIO Disable Register         	     
- 创CSP_REGISTER_T创  PSR :                PIO Status  Register          	     
- 创CSP_REGISTER_T创  ReservedA[1] :     
- 创CSP_REGISTER_T创  OER :                Output Enable  Register       	     
- 创CSP_REGISTER_T创  ODR :                Output Disable Register      	     
- 创CSP_REGISTER_T创  OSR :                Output Status  Register       	     
- 创CSP_REGISTER_T创  ReservedB[5] :     	
- 创CSP_REGISTER_T创  SODR :               Set    Output Data   Register  	 
- 创CSP_REGISTER_T创  CODR :               Clear  Output Data   Register  	 
- 创CSP_REGISTER_T创  ODSR :               Output Data Status   Register  	 
- 创CSP_REGISTER_T创  PDSR :               Pin    Data Status   Register       
- 创CSP_REGISTER_T创  MDER :               Multi-Driver Enable  Register 	     
- 创CSP_REGISTER_T创  MDDR :               Multi-Driver Disable Register	     
- 创CSP_REGISTER_T创  MDSR :               Multi-Driver Status  Register 	     
- 创CSP_REGISTER_T创  ReservedC[1] :     
- 创CSP_REGISTER_T创     ECR :             Enable Clock Register                 
- 创CSP_REGISTER_T创     DCR :             Disable Clock Register                
- 创CSP_REGISTER_T创     PMSR :            Power Management Status Register      
- 创CSP_REGISTER_T创     ReservedD :
- 创CSP_REGISTER_T创     CR :              Control Register                      
- 创CSP_REGISTER_T创     MR :              Mode Register                         
- 创CSP_REGISTER_T创     ReservedE :      
- 创CSP_REGISTER_T创     CSR :             Clear Status Register                 
- 创CSP_REGISTER_T创     SR :              Status Register                       
- 创CSP_REGISTER_T创     IER :             Interrupt Enable Register             
- 创CSP_REGISTER_T创     IDR :             Interrupt Disable Register            
- 创CSP_REGISTER_T创     IMR :             Interrupt Mask Register               
- 创CSP_PWM_CHANNEL_T创  CHANNEL[NB_PWM_CHANNEL] :   PWM Channels              
*******************************************************************************/
typedef struct 
{
  CSP_REGISTER_T  PER;               /* PIO Enable  Register          	     */
  CSP_REGISTER_T  PDR;               /* PIO Disable Register         	     */
  CSP_REGISTER_T  PSR;               /* PIO Status  Register          	     */
  CSP_REGISTER_T  ReservedA[1];     
  CSP_REGISTER_T  OER;               /* Output Enable  Register       	     */
  CSP_REGISTER_T  ODR;               /* Output Disable Register      	     */
  CSP_REGISTER_T  OSR;               /* Output Status  Register       	     */
  CSP_REGISTER_T  ReservedB[5];     	
  CSP_REGISTER_T  SODR;              /* Set    Output Data   Register  	     */
  CSP_REGISTER_T  CODR;              /* Clear  Output Data   Register  	     */
  CSP_REGISTER_T  ODSR;              /* Output Data Status   Register  	     */
  CSP_REGISTER_T  PDSR;              /* Pin    Data Status   Register        */
  CSP_REGISTER_T  MDER;              /* Multi-Driver Enable  Register 	     */
  CSP_REGISTER_T  MDDR;              /* Multi-Driver Disable Register	     */
  CSP_REGISTER_T  MDSR;              /* Multi-Driver Status  Register 	     */
  CSP_REGISTER_T  ReservedC[1];     
  CSP_REGISTER_T  ECR;               /* Enable Clock Register                */
  CSP_REGISTER_T  DCR;               /* Disable Clock Register               */
  CSP_REGISTER_T  PMSR;              /* Power Management Status Reg          */
  CSP_REGISTER_T  ReservedD[1];      /* Reserved                             */
  CSP_REGISTER_T  CR;                /* Control Register                     */
  CSP_REGISTER_T  MR;                /* Mode Register                        */
  CSP_REGISTER_T  ReservedE[1];      /* Reserved                             */
  CSP_REGISTER_T  CSR;               /* Clear Status Register                */
  CSP_REGISTER_T  SR;                /* Status Register                      */
  CSP_REGISTER_T  IER;               /* Interrupt Enable Register            */
  CSP_REGISTER_T  IDR;               /* Interrupt Disable Register           */
  CSP_REGISTER_T  IMR;               /* Interrupt Mask Register              */
  CSP_PWM_CHANNEL_T CHANNEL[NB_PWM_CHANNEL]; /* PWM Channels                 */
} CSP_PWM4C_T;


/******************************************************************************
* PWM PIO Registers PER, PDR, PSR, OER, ODR, OSR, SODR, CODR, ODSR, PDSR
*                   MDER, MDDR, MDSR, CSR, SR, IER, IDR, IMR
******************************************************************************/  
#define PIOPWM0     ( 0x01 << 16 )          /* PWM I/O 0                        */
#define PIOPWM1     ( 0x01 << 17 )          /* PWM I/O 1                        */
#define PIOPWM2     ( 0x01 << 18 )          /* PWM I/O 2                        */
#define PIOPWM3     ( 0x01 << 19 )          /* PWM I/O 3                        */

/******************************************************************************