📄 csp_spi.h
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/*-----------------------------------------------------------------------------
* EUROPE TECHNOLOGIES Software Support
*------------------------------------------------------------------------------
* The software is delivered "AS IS" without warranty or condition of any
* kind, either express, implied or statutory. This includes without
* limitation any warranty or condition with respect to merchantability or
* fitness for any particular purpose, or against the infringements of
* intellectual property rights of others.
*------------------------------------------------------------------------------
*
* File Name : csp_spi.h
* Description : Definitions, Macros and function declarations for
* Serial Peripheral Interface module
* Library Version : 2.00
* Module Version : 1.XX
*
* +----- (NEW | MODify | ADD | DELete)
* |
* No | When Who What
*-----+---+----------+------------------+--------------------------------------
* 000 NEW 01/05/99 Patrice VILCHEZ Creation
* 001 MOD 01/04/01 Olivier MAZUYER Clean up
* 002 MOD 08/06/01 Frederic SAMSON Clean Up
* 003 MOD 19/10/01 Christophe GARDIN Clean Up
* 004 MOD 15/03/02 Christophe GARDIN Add Macros
*----------------------------------------------------------------------------*/
#ifndef CSP_SPI_H
#define CSP_SPI_H
/******************************************************************************
************************** SPI Structure Definition ***************************
******************************************************************************/
/* Number of SPI Chips Select */
#define NB_SPI_CS 4u
/* Chip Select */
#define CS0 0u
#define CS1 1u
#define CS2 2u
#define CS3 3u
/******************************************************************************
* SPI Chip Select Structure
******************************************************************************/
/*******************************************************************************
Type: CSP_SPI_CS_T
Description: SPI Chip Select Structure Definition
Fields:
- 创CSP_REGISTER_T创 CSR : Chips Select Registers
*******************************************************************************/
typedef struct
{
CSP_REGISTER_T CSR; /* Chips Select Registers */
} CSP_SPI_CS_T;
/******************************************************************************
* SPI Structure
******************************************************************************/
/*******************************************************************************
Type: CSP_SPI_T
Description: SPI Structure Definition
Fields:
- 创CSP_REGISTER_T创 PER : PIO Enable Register
- 创CSP_REGISTER_T创 PDR : PIO Disable Register
- 创CSP_REGISTER_T创 PSR : PIO Status Register
- 创CSP_REGISTER_T创 ReservedA :
- 创CSP_REGISTER_T创 OER : Output Enable Register
- 创CSP_REGISTER_T创 ODR : Output Disable Register
- 创CSP_REGISTER_T创 OSR : Output Status Register
- 创CSP_REGISTER_T创 ReservedB[5] :
- 创CSP_REGISTER_T创 SODR : Set Output Data Register
- 创CSP_REGISTER_T创 CODR : Clear Output Data Register
- 创CSP_REGISTER_T创 ODSR : Output Data Status Register
- 创CSP_REGISTER_T创 PDSR : Pin Data Status Register
- 创CSP_REGISTER_T创 MDER : Multi-Driver Enable Register
- 创CSP_REGISTER_T创 MDDR : Multi-Driver Disable Register
- 创CSP_REGISTER_T创 MDSR : Multi-Driver Status Register
- 创CSP_REGISTER_T创 ReservedC :
- 创CSP_REGISTER_T创 ECR : Enable Clock Register
- 创CSP_REGISTER_T创 DCR : Disable Clock Register
- 创CSP_REGISTER_T创 PMSR : Power management Status Register
- 创CSP_REGISTER_T创 ReservedD :
- 创CSP_REGISTER_T创 CR : Control Register
- 创CSP_REGISTER_T创 MR : Mode Register
- 创CSP_REGISTER_T创 ReservedE[2] :
- 创CSP_REGISTER_T创 SR : Status Register
- 创CSP_REGISTER_T创 IER : Interrupt Enable Register
- 创CSP_REGISTER_T创 IDR : Interrupt Disable Register
- 创CSP_REGISTER_T创 IMR : Interrupt Mask Register
- 创CSP_REGISTER_T创 RDR : Receive Data Register
- 创CSP_REGISTER_T创 TDR : Transmit Data Register
- 创CSP_REGISTER_T创 ReservedF[2] :
- 创CSP_SPI_CS_T创 CS[NB_SPI_CS] : Chips Select Registers
*******************************************************************************/
typedef struct
{
CSP_REGISTER_T PER; /* PIO Enable Register */
CSP_REGISTER_T PDR; /* PIO Disable Register */
CSP_REGISTER_T PSR; /* PIO Status Register */
CSP_REGISTER_T ReservedA;
CSP_REGISTER_T OER; /* Output Enable Register */
CSP_REGISTER_T ODR; /* Output Disable Register */
CSP_REGISTER_T OSR; /* Output Status Register */
CSP_REGISTER_T ReservedB[5];
CSP_REGISTER_T SODR; /* Set Output Data Register */
CSP_REGISTER_T CODR; /* Clear Output Data Register */
CSP_REGISTER_T ODSR; /* Output Data Status Register */
CSP_REGISTER_T PDSR; /* Pin Data Status Register */
CSP_REGISTER_T MDER; /* Multi-Driver Enable Register */
CSP_REGISTER_T MDDR; /* Multi-Driver Disable Register */
CSP_REGISTER_T MDSR; /* Multi-Driver Status Register */
CSP_REGISTER_T ReservedC;
CSP_REGISTER_T ECR; /* Enable Clock Register */
CSP_REGISTER_T DCR; /* Disable Clock Register */
CSP_REGISTER_T PMSR; /* Power management Status Register */
CSP_REGISTER_T ReservedD;
CSP_REGISTER_T CR; /* Control Register */
CSP_REGISTER_T MR; /* Mode Register */
CSP_REGISTER_T ReservedE[2];
CSP_REGISTER_T SR; /* Status Register */
CSP_REGISTER_T IER; /* Interrupt Enable Register */
CSP_REGISTER_T IDR; /* Interrupt Disable Register */
CSP_REGISTER_T IMR; /* Interrupt Mask Register */
CSP_REGISTER_T RDR; /* Receive Data Register */
CSP_REGISTER_T TDR; /* Transmit Data Register */
CSP_REGISTER_T ReservedF[2];
CSP_SPI_CS_T CS[NB_SPI_CS]; /* Chips Select Registers */
} CSP_SPI_T;
/******************************************************************************
************************** SPI Registers Definition ***************************
******************************************************************************/
/******************************************************************************
* PER, PDR, PSR, OER, ODR, OSR, :
* SODR, CODR, ODSR, PDSR, MDER, MDDR : SPI PIO Registers, Status Register and
* MDSR, SR, IER, IDR, IMR : Interrupt Registers
******************************************************************************/
#define SPCK (0x01ul << 16) /* SCK as Open Drain */
#define MISO (0x01ul << 17) /* MISO as Open Drain */
#define MOSI (0x01ul << 18) /* MOSI as Open Drain */
#define NPCS0 (0x01ul << 19) /* NPCS0 as Open Drain */
#define NPCS1 (0x01ul << 20) /* NPCS1 as Open Drain */
#define NPCS2 (0x01ul << 21) /* NPCS2 as Open Drain */
#define NPCS3 (0x01ul << 22) /* NPCS3 as Open Drain */
/******************************************************************************
* ECR, DCR, PMSR : SPI Power Management Registers
******************************************************************************/
#define PIO (0x01ul << 0) /* PIO Clock */
#define SPI (0x01ul << 1) /* SPI Clock */
/******************************************************************************
* CR : SPI Control Register
******************************************************************************/
#define SWRST (0x01ul << 0) /* SPI Software Reset */
#define SPIEN (0x01ul << 1) /* SPI Enable Command */
#define SPIDIS (0x01ul << 2) /* SPI Disable Command */
/******************************************************************************
* MR : SPI Mode Register
******************************************************************************/
/* MSTR : Master / Slave Mode */
#define MSTR (0x01ul << 0) /* MSTR Mask */
#define SLAVE (0x00ul << 0) /* Slave Mode */
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