📄 csp_adc8c.h
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/*-----------------------------------------------------------------------------
* EUROPE TECHNOLOGIES Software Support
*------------------------------------------------------------------------------
* The software is delivered "AS IS" without warranty or condition of any
* kind, either express, implied or statutory. This includes without
* limitation any warranty or condition with respect to merchantability or
* fitness for any particular purpose, or against the infringements of
* intellectual property rights of others.
*------------------------------------------------------------------------------
*
* File Name : csp_adc8c.h
* Description : Definitions, Macros and function declarations for
* Analog to Digital Converter 8 channels module
* Library Version : 2.00
* Module Version : 1.XX
*
* +----- (NEW | MODify | ADD | DELete)
* |
* No | When Who What
*-----+---+----------+------------------+--------------------------------------
* 000 NEW 01/05/99 Patrice VILCHEZ Creation
* 001 MOD 01/04/01 Olivier MAZUYER Clean up
* 002 MOD 08/06/01 Frederic SAMSON Clean Up
* 003 ADD 07/08/01 Frederic SAMSON Add CSP_ADCClearInterrupt function
* 004 MOD 23/10/01 Christophe GARDIN Clean Up
* 005 MOD 15/03/02 Christophe GARDIN Add macros and bits
*----------------------------------------------------------------------------*/
#ifndef CSP_ADC8C_H
#define CSP_ADC8C_H
/******************************************************************************
************************* ADC8C Structure Definition **************************
******************************************************************************/
/*******************************************************************************
Type: CSP_ADC8C_T
Description: ADC4C Structure Definition
Fields:
- 创CSP_REGISTER_T创 ReservedA[20] :
- 创CSP_REGISTER_T创 ECR : Clock Enable Register
- 创CSP_REGISTER_T创 DCR : Clock Disable Register
- 创CSP_REGISTER_T创 PMSR : Power Management Status Register
- 创CSP_REGISTER_T创 ReservedB :
- 创CSP_REGISTER_T创 CR : Control Register
- 创CSP_REGISTER_T创 MR : Mode Register
- 创CSP_REGISTER_T创 CMR : Conversion Mode Register
- 创CSP_REGISTER_T创 CSR : Clear Status Register
- 创CSP_REGISTER_T创 SR : Status Register
- 创CSP_REGISTER_T创 IER : Interrupt Enable Register
- 创CSP_REGISTER_T创 IDR : Interrupt Disable Register
- 创CSP_REGISTER_T创 IMR : Interrupt Mask Register
- 创CSP_REGISTER_T创 DR : Convert Data Register
- 创CSP_REGISTER_T创 ReservedC[2] :
- 创CSP_REGISTER_T创 TSTR : Test Mode Register
*******************************************************************************/
typedef struct
{
CSP_REGISTER_T ReservedA[20];
CSP_REGISTER_T ECR; /* Clock Enable Register */
CSP_REGISTER_T DCR; /* Clock Disable Register */
CSP_REGISTER_T PMSR; /* Power Management Status Register */
CSP_REGISTER_T ReservedB;
CSP_REGISTER_T CR; /* Control Register */
CSP_REGISTER_T MR; /* Mode Register */
CSP_REGISTER_T CMR; /* Conversion Mode Register */
CSP_REGISTER_T CSR; /* Clear Status Register */
CSP_REGISTER_T SR; /* Status Register */
CSP_REGISTER_T IER; /* Interrupt Enable Register */
CSP_REGISTER_T IDR; /* Interrupt Disable Register */
CSP_REGISTER_T IMR; /* Interrupt Mask Register */
CSP_REGISTER_T DR; /* Convert Data Register */
CSP_REGISTER_T ReservedC[3];
CSP_REGISTER_T TSTR; /* Test Mode Register */
} CSP_ADC8C_T;
/******************************************************************************
************************* ADC8C Registers Definition **************************
******************************************************************************/
/******************************************************************************
* ECR, DCR, PMSR : ADC8C Power Management Registers
******************************************************************************/
#define ADC (0x01ul << 1) /* ADC Clock */
/******************************************************************************
* CR : ADC8C Control Register
******************************************************************************/
#define SWRST (0x01ul << 0) /* Software Reset */
#define ADCEN (0x01ul << 1) /* ADC Enable */
#define ADCDIS (0x01ul << 2) /* ADC Disable */
#define START (0x01ul << 3) /* Start Conversion */
#define STOP (0x01ul << 4) /* Stop Conversion */
/******************************************************************************
* MR : ADC8C Mode Register
******************************************************************************/
/* PRVAL : Preload Value */
#define PRLVAL_MASK (0x1Ful << 0) /* Mask */
#define PRLVAL(val) (((val) & 0x1Ful) << 0) /* Writing Macro */
#define STOPEN (0x01ul << 6) /* Stop Enable */
/* STARTTIME : Start-up Time value */
#define STARTUPTIME_MASK (0xFFul << 8) /* Mask */
#define STARTUPTIME(val) (((val) & 0xFFul) << 8) /* Writing Macro */
/* NBRCH : Number of conversions */
#define NBRCH (0x07ul << 16) /* NBRCH Mask */
#define NBRCH1 (0x00ul << 16) /* 1 conversion */
#define NBRCH2 (0x01ul << 16) /* 2 conversions */
#define NBRCH3 (0x02ul << 16) /* 3 conversions */
#define NBRCH4 (0x03ul << 16) /* 4 conversions */
#define NBRCH5 (0x04ul << 16) /* 5 conversions */
#define NBRCH6 (0x05ul << 16) /* 6 conversions */
#define NBRCH7 (0x06ul << 16) /* 7 conversions */
#define NBRCH8 (0x07ul << 16) /* 8 conversions */
#define CONTCV (0x01ul << 19) /* Continuous Conversion */
/******************************************************************************
* CMR : ADC8C Conversion Mode Register
******************************************************************************/
/* CV : Input Selection */
#define CV1 (0x03ul << 0) /* CV1 Mask */
#define CV2 (0x03ul << 4) /* CV2 Mask */
#define CV3 (0x03ul << 8) /* CV3 Mask */
#define CV4 (0x03ul << 12) /* CV4 Mask */
#define CV5 (0x03ul << 16) /* CV5 Mask */
#define CV6 (0x03ul << 20) /* CV6 Mask */
#define CV7 (0x03ul << 24) /* CV7 Mask */
#define CV8 (0x03ul << 28) /* CV8 Mask */
/* CV1 Input Selection */
#define CV1IN0 (0x00ul << 0) /* Input 0 */
#define CV1IN1 (0x01ul << 0) /* Input 1 */
#define CV1IN2 (0x02ul << 0) /* Input 2 */
#define CV1IN3 (0x03ul << 0) /* Input 3 */
#define CV1IN4 (0x04ul << 0) /* Input 4 */
#define CV1IN5 (0x05ul << 0) /* Input 5 */
#define CV1IN6 (0x06ul << 0) /* Input 6 */
#define CV1IN7 (0x07ul << 0) /* Input 7 */
/* CV2 Input Selection */
#define CV2IN0 (0x00ul << 4) /* Input 0 */
#define CV2IN1 (0x01ul << 4) /* Input 1 */
#define CV2IN2 (0x02ul << 4) /* Input 2 */
#define CV2IN3 (0x03ul << 4) /* Input 3 */
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