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📄 csp_capt.h

📁 IAR 平台ATMEL 的例程, 和说明
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/*-----------------------------------------------------------------------------
*   EUROPE TECHNOLOGIES Software Support
*------------------------------------------------------------------------------
* The software is delivered "AS IS" without warranty or condition of any
* kind, either express, implied or statutory. This includes without
* limitation any warranty or condition with respect to merchantability or
* fitness for any particular purpose, or against the infringements of
* intellectual property rights of others.
*------------------------------------------------------------------------------
*
* File Name       : csp_capt.h
* Description     : Definitions, Macros and function declarations for
*                   Capture module
* Library Version : 2.00
* Module Version  : 1.XX
*
*       +----- (NEW | MODify | ADD | DELete)                                 
*       |                                                                    
*  No   |   When       Who                What               
*-----+---+----------+------------------+--------------------------------------
* 000  NEW  01/05/99   Patrice VILCHEZ    Creation
* 001  MOD  01/04/01   Olivier MAZUYER    Clean up
* 002  MOD  08/06/01   Frederic SAMSON    Clean Up
* 003  MOD  24/10/01   Christophe GARDIN  Clean Up
* 004  MOD  21/11/02   Bruno SALLE		  Modification for SmartCAN1 : add PIO block
*----------------------------------------------------------------------------*/

#ifndef CSP_CAPT_H
#define CSP_CAPT_H

/******************************************************************************
************************ CAPTURE Structure Definition *************************
******************************************************************************/

/*******************************************************************************
Type: CSP_CAPT_T
Description: CAPT Structure Definition
Fields:
- 创CSP_REGISTER_T创  PER :                PIO Enable  Register          	     
- 创CSP_REGISTER_T创  PDR :                PIO Disable Register         	     
- 创CSP_REGISTER_T创  PSR :                PIO Status  Register          	     
- 创CSP_REGISTER_T创  ReservedA[1] :     
- 创CSP_REGISTER_T创  OER :                Output Enable  Register       	     
- 创CSP_REGISTER_T创  ODR :                Output Disable Register      	     
- 创CSP_REGISTER_T创  OSR :                Output Status  Register       	     
- 创CSP_REGISTER_T创  ReservedB[5] :     	
- 创CSP_REGISTER_T创  SODR :               Set    Output Data   Register  	 
- 创CSP_REGISTER_T创  CODR :               Clear  Output Data   Register  	 
- 创CSP_REGISTER_T创  ODSR :               Output Data Status   Register  	 
- 创CSP_REGISTER_T创  PDSR :               Pin    Data Status   Register       
- 创CSP_REGISTER_T创  MDER :               Multi-Driver Enable  Register 	     
- 创CSP_REGISTER_T创  MDDR :               Multi-Driver Disable Register	     
- 创CSP_REGISTER_T创  MDSR :               Multi-Driver Status  Register 	     
- 创CSP_REGISTER_T创  ReservedC[1] :     
- 创CSP_REGISTER_T创  ECR :                Enable Clock Register           
- 创CSP_REGISTER_T创  DCR :                Disable Clock Register          
- 创CSP_REGISTER_T创  PMSR :               Power Management Status Register
- 创CSP_REGISTER_T创  ReservedD :      
- 创CSP_REGISTER_T创  CR :                 Control Register                
- 创CSP_REGISTER_T创  MR :                 Mode Register                   
- 创CSP_REGISTER_T创  ReservedE :      
- 创CSP_REGISTER_T创  CSR :                Clear Status Register           
- 创CSP_REGISTER_T创  SR :                 Status Register                 
- 创CSP_REGISTER_T创  IER :                Interrupt enable Register       
- 创CSP_REGISTER_T创  IDR :                Interrupt Disable Register      
- 创CSP_REGISTER_T创  IMR :                Interrupt Mask Register         
- 创CSP_REGISTER_T创  DR :                 Capture Data Register           
*******************************************************************************/
typedef struct
{
   CSP_REGISTER_T  PER;               /* PIO Enable  Register          	     */
   CSP_REGISTER_T  PDR;               /* PIO Disable Register         	     */
   CSP_REGISTER_T  PSR;               /* PIO Status  Register          	     */
   CSP_REGISTER_T  ReservedA[1];     
   CSP_REGISTER_T  OER;               /* Output Enable  Register       	     */
   CSP_REGISTER_T  ODR;               /* Output Disable Register      	     */
   CSP_REGISTER_T  OSR;               /* Output Status  Register       	     */
   CSP_REGISTER_T  ReservedB[5];     	
   CSP_REGISTER_T  SODR;              /* Set    Output Data   Register  	 */
   CSP_REGISTER_T  CODR;              /* Clear  Output Data   Register  	 */
   CSP_REGISTER_T  ODSR;              /* Output Data Status   Register  	 */
   CSP_REGISTER_T  PDSR;              /* Pin    Data Status   Register       */
   CSP_REGISTER_T  MDER;              /* Multi-Driver Enable  Register 	     */
   CSP_REGISTER_T  MDDR;              /* Multi-Driver Disable Register	     */
   CSP_REGISTER_T  MDSR;              /* Multi-Driver Status  Register 	     */
   CSP_REGISTER_T  ReservedC[1];     
   CSP_REGISTER_T  ECR;               /* Enable Clock Register               */
   CSP_REGISTER_T  DCR;               /* Disable Clock Register              */
   CSP_REGISTER_T  PMSR;              /* Power Management Status Register    */
   CSP_REGISTER_T  ReservedD;      
   CSP_REGISTER_T  CR;                /* Control Register                    */
   CSP_REGISTER_T  MR;                /* Mode Register                       */
   CSP_REGISTER_T  ReservedE;      
   CSP_REGISTER_T  CSR;               /* Clear Status Register               */
   CSP_REGISTER_T  SR;                /* Status Register                     */
   CSP_REGISTER_T  IER;               /* Interrupt enable Register           */
   CSP_REGISTER_T  IDR;               /* Interrupt Disable Register          */
   CSP_REGISTER_T  IMR;               /* Interrupt Mask Register             */
   CSP_REGISTER_T  DR;                /* Capture Data Register               */
} CSP_CAPT_T;


/******************************************************************************
************************ CAPTURE Registers Definition *************************
******************************************************************************/

/******************************************************************************
* PER, PDR, PSR, OER, ODR, OSR, SODR, CODR, ODSR, PDSR, MDER, MDDR, MDSR, CSR, 
  SR, IER, IDR, IMR : CAPTURE PIO management
******************************************************************************/
#define CAPTPIN			   (0x01ul << 16)  /* CAPTURE Pin                    */

/******************************************************************************
* ECR, DCR, PMSR : CAPTURE Power Management Registers
******************************************************************************/
#define CAP                (0x01ul << 1)  /* CAPTURE Clock                   */

/******************************************************************************
* CR : CAPTURE Control Register 
******************************************************************************/
#define SWRST              (0x01ul << 0)  /* CAPTURE Software Reset          */
#define CAPEN              (0x01ul << 1)  /* CAPTURE Enable                  */
#define CAPDIS             (0x01ul << 2)  /* CAPTURE Disable                 */
#define STARTCAPT          (0x01ul << 3)  /* Start Capture                   */

/******************************************************************************
* MR : CAPTURE Mode Register
******************************************************************************/
/* PRESCALAR : Counter Clock Prescalar                                       */
#define PRESCALAR_MASK        (0x0Ful << 0)              /* Mask             */   
#define CAPT_PRESCALAR(val)   (((val) & 0x0Ful) << 0)    /* Writing Macro    */ 

#define MEASMODE_POS_NEG   (0x00ul << 4)  /* Measure Between Positive and Negative Edge */
#define MEASMODE_POS       (0x02ul << 4)  /* Measure Between Positive Edge   */
#define MEASMODE_NEG       (0x03ul << 4)  /* Measure Between Negative Edge   */
#define OVERMODE           (0x01ul << 6)  /* Overrun Mode                    */
#define ONESHOT            (0x01ul << 7)  /* One Shot                        */

/******************************************************************************
* CSR, SR, IER, IDR, IMR : CAPTURE Status and Interrupt Registers 
******************************************************************************/
#define PDCEND             (0x01ul << 0)  /* PDC End                         */
#define OVERRUN            (0x01ul << 1)  /* Over Run                        */
#define OVERFLOW           (0x01ul << 2)  /* Over Flow                       */

/* SR, IER, IDR, IMR Registers only                                          */
#define DATACAPT           (0x01ul << 3)  /* Data Captured                   */

/* SR Register Only                                                          */
#define CAPENS             (0x01ul << 8)  /* Capture Enable Status           */

/******************************************************************************
* DR : CAPTURE Data Register
******************************************************************************/
/* DURATION : CAPTURE duration                                               */
#define DURATION_MASK      (0x7FFFul << 0)               /* Mask             */
#define DURATION(val)      (((val) & 0x7FFFul) << 0)     /* Writing Macro    */

/* LEVEL : Level Measured                                                    */
#define LEVEL              (0x01ul << 15) /* LEVEL Mask                      */
#define LEVEL_HIGHT        (0x01ul << 15) /* Duration Concerns High Level    */
#define LEVEL_LOW          (0x00ul << 15) /* Duration Concerns Low Level     */


/******************************************************************************
************************* CAPTURE Macros Definition ***************************
******************************************************************************/
/* PER, PDR, PSR : PIO control Registers                                     */
#define CSP_CAPT_SET_PER(capt, val)  ((capt)->PER = (val))        /* Enable  */
#define CSP_CAPT_SET_PDR(capt, val)  ((capt)->PDR = (val))        /* Disable */
#define CSP_CAPT_GET_PSR(capt)       ((capt)->PSR)                /* Status  */

/* OER, ODR, OSR : Output Registers                                          */
#define CSP_CAPT_SET_OER(capt, val)  ((capt)->OER = (val))        /* Enable  */
#define CSP_CAPT_SET_ODR(capt, val)  ((capt)->ODR = (val))        /* Disable */
#define CSP_CAPT_GET_OSR(capt)       ((capt)->OSR)                /* Status  */

/* SODR, CODR, ODSR, PDSR : Output Data Registers                            */
#define CSP_CAPT_SET_SODR(capt, val) ((capt)->SODR = (val))       /* Set     */
#define CSP_CAPT_SET_CODR(capt, val) ((capt)->CODR = (val))       /* Clear   */
#define CSP_CAPT_GET_ODSR(capt)      ((capt)->ODSR)               /* Status  */
#define CSP_CAPT_GET_PDSR(capt)      ((capt)->PDSR)               /* Pin Status */

/* MDER, MDDR, MDSR :  Multi-Driver Registers                                */
#define CSP_CAPT_SET_MDER(capt, val) ((capt)->MDER = (val))       /* Enable  */
#define CSP_CAPT_SET_MDDR(capt, val) ((capt)->MDDR = (val))       /* Disable */
#define CSP_CAPT_GET_MDSR(capt)      ((capt)->MDSR)               /* Status  */


/* ECR, DCR, PMSR : CAPTURE Power Management Registers                       */
#define CSP_CAPT_SET_ECR(capt, val)       ((capt)->ECR = (val))   /* Enable  */
#define CSP_CAPT_SET_DCR(capt, val)       ((capt)->DCR = (val))   /* Disable */
#define CSP_CAPT_GET_PMSR(capt)           ((capt)->PMSR)          /* Status  */

/* CR : CAPTURE Control Register                                             */
#define CSP_CAPT_SET_CR(capt, val)        ((capt)->CR = (val))

/* MR : CAPTURE Mode Register                                                */
#define CSP_CAPT_GET_MR(capt)             ((capt)->MR)
#define CSP_CAPT_SET_MR(capt, mode)       ((capt)->MR = (mode))

/* CSR, SR : CAPTURE Status Registers                                        */
#define CSP_CAPT_SET_CSR(capt, val)       ((capt)->CSR = (val))   /* Clear   */
#define CSP_CAPT_GET_SR(capt)             ((capt)->SR)            /* Status  */

/* IER, IDR, IMR : CAPTURE Interrupt Registers                               */
#define CSP_CAPT_SET_IER(capt, val)       ((capt)->IER = (val))   /* Enable  */
#define CSP_CAPT_SET_IDR(capt, val)       ((capt)->IDR = (val))   /* Disable */
#define CSP_CAPT_GET_IMR(capt)            ((capt)->IMR)           /* Mask    */

/* DR : CAPTURE Data Register                                                */
#define CSP_CAPT_GET_DR(capt)             ((capt)->DR)


/******************************************************************************
******************* CAPTURE External Functions Declaration ********************
******************************************************************************/
extern void CSP_CAPTInit(CSP_CAPT_T *const capt, U32_T mode);
extern void CSP_CAPTClose(CSP_CAPT_T *const capt);
extern void CSP_CAPTConfigInterrupt(CSP_CAPT_T *const capt, U32_T int_mode, U32_T int_mask, U32_T callback);
extern void CSP_CAPTEnable(CSP_CAPT_T *const capt);
extern void CSP_CAPTDisable(CSP_CAPT_T *const capt);
extern void CSP_CAPTStart(CSP_CAPT_T *const capt);
extern void CSP_CAPTPioInit(CSP_CAPT_T *const capt, U32_T pio_mask, U32_T output_pio);
extern U32_T CSP_CAPTPioGetStatus(CSP_CAPT_T *const capt);
extern void CSP_CAPTPioClear(CSP_CAPT_T *const capt, U32_T pio_mask);
extern void CSP_CAPTPioSet(CSP_CAPT_T *const capt, U32_T pio_mask);

#endif   /* CSP_CAPT_H */

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