mmu_pagetable.s79

IAR 开发环境的Cirrus Logic的例程

/*
 * $Revision: 1.1 $
 */

; The MMU page table.  The virtual memory map created by this page table is:
;  0x00000000 - 0x00ffffff => 16M bytes DRAM
;  0x01000000 - 0x017fffff => 8M bytes Flash Bank1 (nCS0)
;  0x01800000 - 0x01ffffff => 8M bytes Flash Bank0 (nCS0) 			 
;  0x10000000 - 0x1fffffff => NAND FLASH interface (nCS1)
;  0x20000000 - 0x2fffffff => Ethernet Controller
;  0x30000000 - 0x3fffffff => Parallel port interface (nCS1), keyboards, etc.
;  0x40000000 - 0x4fffffff => USB Controller
;  0x50000000 - 0x5fffffff => Expansion
;  0x60000000 - 0x600095ff => 40K of internal SRAM (only 37.5K exists)
;  0x70000000 - 0x7000007f => On-chip boot ROM	
;  0x80000000 - 0x80002fff => EP7209 internal registers
;
; PageTable is the level 1 page table.  This really should have all 4K entries
; populated, but we simply populate the first 2K (8Kbytes) since that is all we use.

  RSEG PAGETABLE:CONST(14)
  DATA
  EXPORT PageTable

PageTable:

; 0x00000000: 16MB of DRAM, repeated twice
; First physical address from  0xc0000000 - 0xc0800000
; Second physical address from 0xc1000000 - 0xc1800000

XCount SETA 0xc0000c1e                    ;16mg ram
  rept 8
  DCD     XCount
XCount SETA XCount + 0x00100000
  endr

XCount SETA 0xc1000c1e
  rept 8
  DCD XCount
XCount SETA XCount + 0x00100000
  endr
    
; 0x01000000 16MB of Flash
; Physical location 0x00000000 - 0x00ffffff

XCount SETA 0x00000c12
  rept 16
  DCD XCount
XCount SETA XCount + 0x00100000
  endr

; Define memory from 0x0200.0000 - 0x0fff.ffff as inaccessible (224 MB)
XCount SETA 0x02000000
  rept 224
  DCD XCount
XCount SETA XCount + 0x00100000
  endr

; 0x10000000 - 0x5fffffff (256MB * 5 = 1.25GB of direct mapped r/w memory)
; 1280 entries (5120 bytes)

XCount SETA 0x10000c12
  rept 1280
  DCD XCount
XCount SETA XCount + 0x00100000
  endr
    
; 0x60000000 (1.5GB): 37.5K of SRAM (a full Meg is accessible)
  DCD 0x60000c1e

; 0x60100000 (1.5GB + 1MB): 255MB of inaccessible memory

XCount SETA 0x60100000
  rept 255
  DCD XCount
XCount SETA XCount + 0x00100000
  endr

; 0x70000000 (1.75GB): 128 bytes of boot ROM (a full Meg is accessible)
    DCD 0x70000c1e

; 0x70100000 (1.75GB + 1MB): 255MB of inaccessible memory

XCount SETA 0x70100000
  rept 255
  DCD XCount
XCount SETA XCount + 0x00100000
  endr

; 0x80000000 (2GB): 1MB of hardware registers, using level 2 page tables
  DCD HwLevel2Page+0x00000011

; 0x80100000 (2GB + 1MB): 1023MB of inaccessible memory

XCount SETA 0x80100000
  rept 255
  DCD XCount
XCount SETA XCount + 0x00100000
  endr

 
; Level2 is the level 2 page table.  This maps the internal registers only

  RSEG    PAGETABLE_HW:CONST(10)
  DATA
HwLevel2Page:

; 0x80000000 (2GB): non-cacheable area of 1MB memory, some inaccessible
; Generally only the bottom 8k is accessed
  DCD 0x80000ff2
  DCD 0x80001ff2
  DCD 0x80002ff2
  DCD 0x80003000
  DCD 0x80004ff2
  DCD 0x80005ff2
  DCD 0x80006000
  DCD 0x80007000
  DCD 0x80008ff2
  DCD 0x80009ff2
  DCD 0x8000A000
  DCD 0x8000B000
  DCD 0x8000Cff2
  DCD 0x8000Dff2

XCount SETA 0x8000E000
  rept 256-14
  DCD  XCount
XCount SETA XCount + 0x00001000
  endr

  END