cdb89712_cstartup.s79

IAR 开发环境的Cirrus Logic的例程

;-----------------------------------------------------------------------------
; This file contains the startup code used by the ICCARM C compiler.
;
; The modules in this file are included in the libraries, and may be replaced
; by any user-defined modules that define the PUBLIC symbol _program_start or
; a user defined start symbol.
; To override the cstartup defined in the library, simply add your modified
; version to the workbench project.
;
; All code in the modules (except ?RESET) will be placed in the ICODE segment.
;
; $Revision: 1.4 $
;
;-----------------------------------------------------------------------------
	
;
; Naming covention of labels in this file:
;
;  ?xxx	  - External labels only accessed from assembler.
;  __xxx  - External labels accessed from or defined in C.
;  xxx	  - Labels local to one module (note: this file contains 
;           several modules).
;  main	  - The starting point of the user program.
;

;---------------------------------------------------------------
; Macros and definitions for the whole file
;---------------------------------------------------------------

; Mode, correspords to bits 0-5 in CPSR
MODE_BITS	DEFINE	0x1F		; Bit mask for mode bits in CPSR
USR_MODE	DEFINE	0x10		; User mode
FIQ_MODE	DEFINE	0x11		; Fast Interrupt Request mode
IRQ_MODE	DEFINE	0x12		; Interrupt Request mode
SVC_MODE	DEFINE	0x13		; Supervisor mode
ABT_MODE	DEFINE	0x17		; Abort mode
UND_MODE	DEFINE	0x1B		; Undefined Instruction mode
SYS_MODE	DEFINE	0x1F		; System mode
	

;---------------------------------------------------------------
; ?RESET
; Reset Vector.
; Normally, segment INTVEC is linked at address 0.
; For debugging purposes, INTVEC may be placed at other
; addresses.
; A debugger that honors the entry point will start the
; program in a normal way even if INTVEC is not at address 0.
;---------------------------------------------------------------

		MODULE	?RESET
		COMMON	INTVEC:CODE:NOROOT(2)
		PUBLIC  __program_start
		EXTERN	?cstartup
		EXTERN	undef_handler, swi_handler, prefetch_handler
		EXTERN	data_handler, irq_handler, fiq_handler
		CODE32	; Always ARM mode after reset	
		org	0x00
__program_start
		ldr	pc,=?cstartup  ; Absolute jump can reach 4 GByte
;		ldr	b,?cstartup    ; Relative branch allows remap, limited to 32 MByte
		org	0x04
;		ldr	pc,=undef_handler
		org	0x08
;		ldr	pc,=swi_handler
		org	0x0c
;		ldr	pc,=prefetch_handler
		org	0x10
;		ldr	pc,=data_handler
		org	0x18
;		ldr	pc,=irq_handler
		org	0x1c
;		ldr	pc,=fiq_handler

		; Constant table entries (for ldr pc) will be placed at 0x20
		org	0x20
		LTORG
;		ENDMOD	__program_start
                ENDMOD


;---------------------------------------------------------------
; ?CSTARTUP
;---------------------------------------------------------------
		MODULE	?CSTARTUP

		RSEG	IRQ_STACK:DATA(2)
		RSEG	SVC_STACK:DATA:NOROOT(2)
		RSEG	CSTACK:DATA(2)
		RSEG	ICODE:CODE:NOROOT(2)
		PUBLIC	?cstartup
		EXTERN	?main

; Execution starts here.
; After a reset, the mode is ARM, Supervisor, interrupts disabled.


		CODE32
?cstartup

; Add initialization nedded before setup of stackpointers here

; =========================================
; Cirrus CDB89712 specific code starts here
; =========================================

  ;
  ; Setup the MMU for 32 bit code and data.
  ;
  ldr r0, =0x00000070
  mcr p15, 0, r0, c1, c0

  ; Disable all interrupts in the interrupt controller.
  ldr r0, =0x00000000
  ldr r2, =0x80000280
  str r0, [r2]                    ; INTMR1 = 0
  ldr r2, =0x80001280
  str r0, [r2]                    ; INTMR2 = 0

  ; Setup SDRAM CONTROLLER
  ldr r0, =0x522                  ; 64 Mbits configuration.
  ldr r2, =0x80002300
  str r0, [r2]                    ; SDCONF = 0x522
  ; Setup SDRAM refresh
  ldr r0, =0x100
  ldr r2, =0x80002340
  str r0, [r2]                    ; SDRFPR = 0x100

  ; Setup 32 bit SDRAM bus.
  ldr r0, =0x0
  ldr r2, =0x80001100
  str r0, [r2]                    ; SYSCON2 = 0
     
  ; Set 73.7 MHz processor clock speed (default is 18.4 MHz)
  ldr r0, =0x6
  ldr r2, =0x80002200
  str r0, [r2]                    ; SYSCON3 = 0

  ; nCS0 = NOR FLASH, 32-bit, 3 wait states
  ; nCS1 = NAND FLASH, 32-bit, 2 wait states
  ; nCS2 = Ethernet, 16-bit, 8 wait states (was 32-bit =0x00)
  ; nCS3 = Parallel/Keyboard/GPIOs, 32-bit, 1 wait state
  ldr r0, =0x3c011814
  ldr r2, =0x80000180
  str r0, [r2]                    ; MEMCFG1 = 0x3c011814
  
  ; nCS4 = USB, 8-bit, 1 wait state, 2 w/s random (was 32-bit, =0x3c)
  ; nCS5 = Unused/general purpose, 32-bit, 8 wait states
  ; boot rom and internal SRAM are ignored
  ldr r0, =0x0000001e
  ldr r2, =0x800001c0
  str r0, [r2]                    ; MEMCFG2 = 0x0000001e

  ; Set up the MMU.
  ; Flush the cache and TLB.
  ldr r0, =0x00000000
  mcr p15, 0, r0, c5, c0
  mcr p15, 0, r0, c7, c0

  ; Set user mode access for all 16 domains.
  ldr r0, =0x55555555
  mcr p15, 0, r0, c3, c0

  ; Set MMU page table.
  EXTERN  PageTable
  ldr r0, =PageTable
  mcr p15, 0, r0, c2, c0

  ; Before enabling the MMU, the program and the tables must be copied to
  ; physical DRAM starting at location 0xc0000000.  
  ; After the MMU is enabled, the DRAM will be remapped to 0 and the Flash
  ; boot code will remap to 0x010000000.
  ; Only the first 32 Kbytes are copied since this code + MMU tables are <32K
  ; R13 and r14 should be used with care since it stores the stack pointer and 
  ; link address.
  ldr r0, =0x0                    ; Source start address.
  ldr r1, =0x8000                 ; Source stop address.
  ldr r2, =0xc0000000             ; Destination start address.
copy_code:
  ldmia r0!,{r3-r12}              ; Load 10 words to copy.
  stmia r2!,{r3-r12}              ; Store 10 words to new location.
  subs r3,r0,r1                   ; Check if end of copy.
  blt copy_code                   ; If not done, continue.

  ; Enable the MMU.
  ldr  r0, =0x0000007d
  mcr     p15, 0, r0, c1, c0

  ; The first 16 Mbyte is now SDRAM.
  ; There should always be two NOP instructions following the enable or
  ; disable of the MMU.
  mov r0, r0
  mov r0, r0

; =========================================
; Cirrus CDB89712 specific code ends here
; =========================================


; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS. 
; The stack segments must be defined in the linker command file,
; and be declared above.
                mrs     r0,cpsr                             ; Original PSR value
                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
                orr     r0,r0,#IRQ_MODE                     ; Set IRQ mode bits
                msr     cpsr_c,r0                           ; Change the mode
                ldr     sp,=SFE(IRQ_STACK) & 0xFFFFFFF8     ; End of IRQ_STACK
                
                bic     r0,r0,#MODE_BITS                    ; Clear the mode bits
                orr     r0,r0,#SYS_MODE                     ; Set System mode bits
                msr     cpsr_c,r0                           ; Change the mode
                ldr     sp,=SFE(CSTACK) & 0xFFFFFFF8        ; End of CSTACK

#ifdef __ARMVFP__
; Enable the VFP coprocessor.
                mov     r0, #0x40000000                 ; Set EN bit in VFP
                fmxr    fpexc, r0                       ; FPEXC, clear others.

; Disable underflow exceptions by setting flush to zero mode.
; For full IEEE 754 underflow compliance this code should be removed
; and the appropriate exception handler installed.
                mov     r0, #0x01000000		        ; Set FZ bit in VFP
                fmxr    fpscr, r0                       ; FPSCR, clear others.
#endif
        
; Add more initialization here


; Continue to ?main for more IAR specific system startup

                ldr     r0,=?main        
                bx      r0        
            
                LTORG
                            
                ENDMOD
            
            
                END