pnpro.v

FPGA中嵌中高级课件,非常有用的课件

`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:    13:13:01 05/26/07
// Design Name:    
// Module Name:    pnpro
// Project Name:   
// Target Device:  
// Tool versions:  
// Description:
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////
module pnpro(clk,ino,pros,proout);
input clk,ino;
 

output pros;
output proout;
reg pros="0";
reg proout="0";
reg [7:0] temp="00000000";
always@ (posedge clk)
begin


if(temp==0)
begin
  if(ino==1)
  begin
  proout<=1'b0;
  pros<=1'b1;
  temp<=temp+1;
  end
  else
  begin
  proout<=1'b1;
  pros<=1'b1;
  temp<=temp+1;
  end
end
else
begin
  if(temp==8'd1) begin
  pros<=1'b0;
  temp<=temp+1;
  end
  else begin
     if(temp<8'd48)begin
     temp<=temp+1;
     pros<=1'b0;
	  end
     else	temp<=0;
   end
end
end


endmodule