clkfp.tan.qmsg

FPGA中嵌中高级课件,非常有用的课件

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 22 -1 0 } } { "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/altera/72/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register state\[4\] register state\[0\] 176.52 MHz 5.665 ns Internal " "Info: Clock \"clk\" has Internal fmax of 176.52 MHz between source register \"state\[4\]\" and destination register \"state\[0\]\" (period= 5.665 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.222 ns + Longest register register " "Info: + Longest register to register delay is 5.222 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns state\[4\] 1 REG LC_X5_Y5_N6 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y5_N6; Fanout = 4; REG Node = 'state\[4\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { state[4] } "NODE_NAME" } } { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.275 ns) + CELL(0.462 ns) 1.737 ns Equal0~147 2 COMB LC_X5_Y5_N2 1 " "Info: 2: + IC(1.275 ns) + CELL(0.462 ns) = 1.737 ns; Loc. = LC_X5_Y5_N2; Fanout = 1; COMB Node = 'Equal0~147'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.737 ns" { state[4] Equal0~147 } "NODE_NAME" } } { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.403 ns) + CELL(0.571 ns) 3.711 ns Equal0~150 3 COMB LC_X5_Y5_N5 4 " "Info: 3: + IC(1.403 ns) + CELL(0.571 ns) = 3.711 ns; Loc. = LC_X5_Y5_N5; Fanout = 4; COMB Node = 'Equal0~150'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.974 ns" { Equal0~147 Equal0~150 } "NODE_NAME" } } { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 35 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.142 ns) + CELL(0.369 ns) 5.222 ns state\[0\] 4 REG LC_X5_Y6_N1 4 " "Info: 4: + IC(1.142 ns) + CELL(0.369 ns) = 5.222 ns; Loc. = LC_X5_Y6_N1; Fanout = 4; REG Node = 'state\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.511 ns" { Equal0~150 state[0] } "NODE_NAME" } } { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.402 ns ( 26.85 % ) " "Info: Total cell delay = 1.402 ns ( 26.85 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.820 ns ( 73.15 % ) " "Info: Total interconnect delay = 3.820 ns ( 73.15 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.222 ns" { state[4] Equal0~147 Equal0~150 state[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.222 ns" { state[4] {} Equal0~147 {} Equal0~150 {} state[0] {} } { 0.000ns 1.275ns 1.403ns 1.142ns } { 0.000ns 0.462ns 0.571ns 0.369ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.388 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.388 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns clk 1 CLK PIN_H5 17 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_H5; Fanout = 17; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(0.574 ns) 2.388 ns state\[0\] 2 REG LC_X5_Y6_N1 4 " "Info: 2: + IC(1.087 ns) + CELL(0.574 ns) = 2.388 ns; Loc. = LC_X5_Y6_N1; Fanout = 4; REG Node = 'state\[0\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.661 ns" { clk state[0] } "NODE_NAME" } } { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns ( 54.48 % ) " "Info: Total cell delay = 1.301 ns ( 54.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.087 ns ( 45.52 % ) " "Info: Total interconnect delay = 1.087 ns ( 45.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { clk state[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { clk {} clk~combout {} state[0] {} } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.388 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.388 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns clk 1 CLK PIN_H5 17 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_H5; Fanout = 17; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(0.574 ns) 2.388 ns state\[4\] 2 REG LC_X5_Y5_N6 4 " "Info: 2: + IC(1.087 ns) + CELL(0.574 ns) = 2.388 ns; Loc. = LC_X5_Y5_N6; Fanout = 4; REG Node = 'state\[4\]'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.661 ns" { clk state[4] } "NODE_NAME" } } { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 31 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns ( 54.48 % ) " "Info: Total cell delay = 1.301 ns ( 54.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.087 ns ( 45.52 % ) " "Info: Total interconnect delay = 1.087 ns ( 45.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { clk state[4] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { clk {} clk~combout {} state[4] {} } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { clk state[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { clk {} clk~combout {} state[0] {} } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { clk state[4] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { clk {} clk~combout {} state[4] {} } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 31 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.208 ns + " "Info: + Micro setup delay of destination is 0.208 ns" {  } { { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 31 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "5.222 ns" { state[4] Equal0~147 Equal0~150 state[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "5.222 ns" { state[4] {} Equal0~147 {} Equal0~150 {} state[0] {} } { 0.000ns 1.275ns 1.403ns 1.142ns } { 0.000ns 0.462ns 0.571ns 0.369ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { clk state[0] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { clk {} clk~combout {} state[0] {} } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { clk state[4] } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { clk {} clk~combout {} state[4] {} } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk clock clock~reg0 5.680 ns register " "Info: tco from clock \"clk\" to destination pin \"clock\" through register \"clock~reg0\" is 5.680 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.388 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.388 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.727 ns) 0.727 ns clk 1 CLK PIN_H5 17 " "Info: 1: + IC(0.000 ns) + CELL(0.727 ns) = 0.727 ns; Loc. = PIN_H5; Fanout = 17; CLK Node = 'clk'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.087 ns) + CELL(0.574 ns) 2.388 ns clock~reg0 2 REG LC_X5_Y5_N9 2 " "Info: 2: + IC(1.087 ns) + CELL(0.574 ns) = 2.388 ns; Loc. = LC_X5_Y5_N9; Fanout = 2; REG Node = 'clock~reg0'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "1.661 ns" { clk clock~reg0 } "NODE_NAME" } } { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 31 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.301 ns ( 54.48 % ) " "Info: Total cell delay = 1.301 ns ( 54.48 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.087 ns ( 45.52 % ) " "Info: Total interconnect delay = 1.087 ns ( 45.52 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { clk clock~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { clk {} clk~combout {} clock~reg0 {} } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.235 ns + " "Info: + Micro clock to output delay of source is 0.235 ns" {  } { { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 31 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.057 ns + Longest register pin " "Info: + Longest register to pin delay is 3.057 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns clock~reg0 1 REG LC_X5_Y5_N9 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y5_N9; Fanout = 2; REG Node = 'clock~reg0'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock~reg0 } "NODE_NAME" } } { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 31 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.603 ns) + CELL(1.454 ns) 3.057 ns clock 2 PIN PIN_K3 0 " "Info: 2: + IC(1.603 ns) + CELL(1.454 ns) = 3.057 ns; Loc. = PIN_K3; Fanout = 0; PIN Node = 'clock'" {  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.057 ns" { clock~reg0 clock } "NODE_NAME" } } { "clkfp.v" "" { Text "E:/技术资料/逻辑设计/中嵌中高级课件/clkfp.v" 23 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.454 ns ( 47.56 % ) " "Info: Total cell delay = 1.454 ns ( 47.56 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.603 ns ( 52.44 % ) " "Info: Total interconnect delay = 1.603 ns ( 52.44 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.057 ns" { clock~reg0 clock } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.057 ns" { clock~reg0 {} clock {} } { 0.000ns 1.603ns } { 0.000ns 1.454ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "2.388 ns" { clk clock~reg0 } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "2.388 ns" { clk {} clk~combout {} clock~reg0 {} } { 0.000ns 0.000ns 1.087ns } { 0.000ns 0.727ns 0.574ns } "" } } { "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/72/quartus/bin/TimingClosureFloorplan.fld" "" "3.057 ns" { clock~reg0 clock } "NODE_NAME" } } { "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/72/quartus/bin/Technology_Viewer.qrui" "3.057 ns" { clock~reg0 {} clock {} } { 0.000ns 1.603ns } { 0.000ns 1.454ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "112 " "Info: Allocated 112 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Wed Sep 24 22:27:36 2008 " "Info: Processing ended: Wed Sep 24 22:27:36 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}